EDN Simulation Results

Tuesday October 07 2025 16:07:43 UTC

GitHub Revision: 0f6fcf0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 0.840s 46.227us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.800s 16.660us 1 1 100.00
V1 csr_rw edn_csr_rw 0.780s 20.024us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 2.170s 593.792us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 0.950s 43.895us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 0.950s 72.470us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.780s 20.024us 1 1 100.00
edn_csr_aliasing 0.950s 43.895us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 1.560s 52.592us 1 1 100.00
V2 csrng_commands edn_genbits 1.560s 52.592us 1 1 100.00
V2 genbits edn_genbits 1.560s 52.592us 1 1 100.00
V2 interrupts edn_intr 0.930s 56.841us 1 1 100.00
V2 alerts edn_alert 1.140s 95.108us 1 1 100.00
V2 errs edn_err 1.030s 24.856us 1 1 100.00
V2 disable edn_disable 0.970s 14.217us 1 1 100.00
edn_disable_auto_req_mode 1.120s 64.461us 1 1 100.00
V2 stress_all edn_stress_all 2.530s 761.084us 1 1 100.00
V2 intr_test edn_intr_test 0.780s 13.035us 1 1 100.00
V2 alert_test edn_alert_test 0.890s 68.040us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 1.850s 73.641us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 1.850s 73.641us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.800s 16.660us 1 1 100.00
edn_csr_rw 0.780s 20.024us 1 1 100.00
edn_csr_aliasing 0.950s 43.895us 1 1 100.00
edn_same_csr_outstanding 0.830s 27.081us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.800s 16.660us 1 1 100.00
edn_csr_rw 0.780s 20.024us 1 1 100.00
edn_csr_aliasing 0.950s 43.895us 1 1 100.00
edn_same_csr_outstanding 0.830s 27.081us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 6.010s 975.789us 1 1 100.00
edn_tl_intg_err 1.290s 185.096us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 0.970s 20.389us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 1.140s 95.108us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 6.010s 975.789us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 6.010s 975.789us 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 6.010s 975.789us 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 6.010s 975.789us 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.140s 95.108us 1 1 100.00
edn_sec_cm 6.010s 975.789us 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.140s 95.108us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 1.290s 185.096us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets