HMAC Simulation Results

Tuesday October 07 2025 16:07:43 UTC

GitHub Revision: 0f6fcf0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 3.600s 2.319ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.850s 100.543us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.720s 14.607us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 7.470s 5.344ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 3.810s 105.923us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.100s 59.971us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.720s 14.607us 1 1 100.00
hmac_csr_aliasing 3.810s 105.923us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 27.240s 3.236ms 1 1 100.00
V2 back_pressure hmac_back_pressure 41.270s 1.076ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 7.650s 390.112us 1 1 100.00
hmac_test_sha384_vectors 6.338m 35.958ms 1 1 100.00
hmac_test_sha512_vectors 6.067m 46.340ms 1 1 100.00
hmac_test_hmac256_vectors 6.150s 853.306us 1 1 100.00
hmac_test_hmac384_vectors 7.480s 511.459us 1 1 100.00
hmac_test_hmac512_vectors 8.150s 1.524ms 1 1 100.00
V2 burst_wr hmac_burst_wr 20.110s 577.359us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 16.160s 237.729us 1 1 100.00
V2 error hmac_error 1.139m 28.367ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.092m 7.567ms 1 1 100.00
V2 save_and_restore hmac_smoke 3.600s 2.319ms 1 1 100.00
hmac_long_msg 27.240s 3.236ms 1 1 100.00
hmac_back_pressure 41.270s 1.076ms 1 1 100.00
hmac_datapath_stress 16.160s 237.729us 1 1 100.00
hmac_burst_wr 20.110s 577.359us 1 1 100.00
hmac_stress_all 7.980s 8.845ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 3.600s 2.319ms 1 1 100.00
hmac_long_msg 27.240s 3.236ms 1 1 100.00
hmac_back_pressure 41.270s 1.076ms 1 1 100.00
hmac_datapath_stress 16.160s 237.729us 1 1 100.00
hmac_wipe_secret 1.092m 7.567ms 1 1 100.00
hmac_test_sha256_vectors 7.650s 390.112us 1 1 100.00
hmac_test_sha384_vectors 6.338m 35.958ms 1 1 100.00
hmac_test_sha512_vectors 6.067m 46.340ms 1 1 100.00
hmac_test_hmac256_vectors 6.150s 853.306us 1 1 100.00
hmac_test_hmac384_vectors 7.480s 511.459us 1 1 100.00
hmac_test_hmac512_vectors 8.150s 1.524ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 3.600s 2.319ms 1 1 100.00
hmac_long_msg 27.240s 3.236ms 1 1 100.00
hmac_back_pressure 41.270s 1.076ms 1 1 100.00
hmac_datapath_stress 16.160s 237.729us 1 1 100.00
hmac_burst_wr 20.110s 577.359us 1 1 100.00
hmac_error 1.139m 28.367ms 1 1 100.00
hmac_wipe_secret 1.092m 7.567ms 1 1 100.00
hmac_test_sha256_vectors 7.650s 390.112us 1 1 100.00
hmac_test_sha384_vectors 6.338m 35.958ms 1 1 100.00
hmac_test_sha512_vectors 6.067m 46.340ms 1 1 100.00
hmac_test_hmac256_vectors 6.150s 853.306us 1 1 100.00
hmac_test_hmac384_vectors 7.480s 511.459us 1 1 100.00
hmac_test_hmac512_vectors 8.150s 1.524ms 1 1 100.00
hmac_stress_all 7.980s 8.845ms 1 1 100.00
V2 stress_all hmac_stress_all 7.980s 8.845ms 1 1 100.00
V2 alert_test hmac_alert_test 0.570s 18.237us 1 1 100.00
V2 intr_test hmac_intr_test 0.630s 31.046us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.600s 421.936us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.600s 421.936us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.850s 100.543us 1 1 100.00
hmac_csr_rw 0.720s 14.607us 1 1 100.00
hmac_csr_aliasing 3.810s 105.923us 1 1 100.00
hmac_same_csr_outstanding 1.410s 474.380us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.850s 100.543us 1 1 100.00
hmac_csr_rw 0.720s 14.607us 1 1 100.00
hmac_csr_aliasing 3.810s 105.923us 1 1 100.00
hmac_same_csr_outstanding 1.410s 474.380us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.960s 47.151us 1 1 100.00
hmac_tl_intg_err 1.470s 98.796us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 1.470s 98.796us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 3.600s 2.319ms 1 1 100.00
V3 stress_reset hmac_stress_reset 1.950s 380.032us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 48.220s 3.581ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 0.820s 32.407us 1 1 100.00
TOTAL 28 28 100.00