I2C Simulation Results

Tuesday October 07 2025 16:07:43 UTC

GitHub Revision: 0f6fcf0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	44.720s	1.422ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	11.820s	2.706ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.840s	55.180us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.680s	47.883us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.090s	1.790ms	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.650s	623.002us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.770s	45.242us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.680s	47.883us	1	1	100.00
		i2c_csr_aliasing	1.650s	623.002us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	4.380s	398.420us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	42.337m	142.172ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	30.770s	3.184ms	1	1	100.00
V2	host_override	i2c_host_override	0.800s	25.504us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	3.232m	4.483ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	24.200s	2.865ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.410s	257.386us	1	1	100.00
		i2c_host_fifo_fmt_empty	5.090s	1.368ms	1	1	100.00
		i2c_host_fifo_reset_rx	4.330s	242.459us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.190m	6.414ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	23.700s	676.207us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.230s	468.218us	1	1	100.00
V2	target_glitch	i2c_target_glitch	3.930s	961.529us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	3.708m	23.081ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.100s	2.729ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	19.310s	5.701ms	1	1	100.00
		i2c_target_intr_smoke	5.620s	1.600ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.040s	549.706us	1	1	100.00
		i2c_target_fifo_reset_tx	1.280s	134.038us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	35.440s	36.952ms	1	1	100.00
		i2c_target_stress_rd	19.310s	5.701ms	1	1	100.00
		i2c_target_intr_stress_wr	25.150s	19.282ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.530s	4.248ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	18.610s	2.653ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	2.210s	7.729ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.330s	724.857us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.900s	1.437ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	0.910s	102.953us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	30.770s	3.184ms	1	1	100.00
		i2c_host_perf_precise	4.891m	5.885ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	23.700s	676.207us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	1.760s	90.669us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.240s	1.681ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.130s	674.246us	1	1	100.00
		i2c_target_nack_txstretch	1.170s	555.436us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	3.010s	1.776ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.870s	6.062ms	1	1	100.00
V2	alert_test	i2c_alert_test	0.800s	15.341us	1	1	100.00
V2	intr_test	i2c_intr_test	0.840s	43.393us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.940s	453.767us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.940s	453.767us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.840s	55.180us	1	1	100.00
		i2c_csr_rw	0.680s	47.883us	1	1	100.00
		i2c_csr_aliasing	1.650s	623.002us	1	1	100.00
		i2c_same_csr_outstanding	0.820s	38.899us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.840s	55.180us	1	1	100.00
		i2c_csr_rw	0.680s	47.883us	1	1	100.00
		i2c_csr_aliasing	1.650s	623.002us	1	1	100.00
		i2c_same_csr_outstanding	0.820s	38.899us	1	1	100.00
V2		TOTAL			34	38	89.47
V2S	tl_intg_err	i2c_tl_intg_err	1.260s	70.406us	1	1	100.00
		i2c_sec_cm	0.780s	539.033us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.260s	70.406us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	2.380s	879.291us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.830s	393.462us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	22.820s	7.906ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			43	50	86.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 3 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.27569367996949859373189926962940116030465930958811386799398344774139722100492
      Line 139, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @ 398420398 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 398420398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.21985142786545875048151144159241278168140669321011100888464703796456735781383
      Line 115, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 142171648816 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 142171648816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.68031843660572913638566122157410858765065810798040473346172835337599156496946
      Line 152, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7905799143 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 7905799143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.19405208776406616955996521402838731857087755854878822814292543989371485728382
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 961528504 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 961528504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.22158089339951100958431037109866658916626884974767533808921664722410432708046
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 393462166 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 97 [0x61])
        UVM_INFO @ 393462166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.3286842680046462646015124543649598589817313626492653917126186684901191120703
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 879291390 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 879291390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.45078153628668275971686247666611206017550547067115184265254732198475196481883
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 555435651 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 555435651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---