KEYMGR Simulation Results

Tuesday October 07 2025 16:07:43 UTC

GitHub Revision: 0f6fcf0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 1.700s 54.743us 1 1 100.00
V1 random keymgr_random 34.220s 9.864ms 1 1 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 0.910s 17.488us 1 1 100.00
V1 csr_rw keymgr_csr_rw 1.160s 22.107us 1 1 100.00
V1 csr_bit_bash keymgr_csr_bit_bash 5.020s 137.084us 1 1 100.00
V1 csr_aliasing keymgr_csr_aliasing 4.180s 1.589ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 1.170s 60.621us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 1.160s 22.107us 1 1 100.00
keymgr_csr_aliasing 4.180s 1.589ms 1 1 100.00
V1 TOTAL 7 7 100.00
V2 cfgen_during_op keymgr_cfg_regwen 2.410s 137.181us 1 1 100.00
V2 sideload keymgr_sideload 4.750s 568.973us 1 1 100.00
keymgr_sideload_kmac 2.350s 383.159us 1 1 100.00
keymgr_sideload_aes 1.980s 140.326us 1 1 100.00
keymgr_sideload_otbn 3.760s 156.493us 1 1 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 2.130s 87.047us 1 1 100.00
V2 lc_disable keymgr_lc_disable 3.070s 153.780us 1 1 100.00
V2 kmac_error_response keymgr_kmac_rsp_err 2.410s 235.232us 1 1 100.00
V2 invalid_sw_input keymgr_sw_invalid_input 4.460s 213.532us 1 1 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 2.100s 76.612us 1 1 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 1.340s 210.516us 1 1 100.00
V2 stress_all keymgr_stress_all 48.150s 2.532ms 1 1 100.00
V2 intr_test keymgr_intr_test 0.840s 10.111us 1 1 100.00
V2 alert_test keymgr_alert_test 0.950s 29.915us 1 1 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 2.160s 305.089us 1 1 100.00
V2 tl_d_illegal_access keymgr_tl_errors 2.160s 305.089us 1 1 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 0.910s 17.488us 1 1 100.00
keymgr_csr_rw 1.160s 22.107us 1 1 100.00
keymgr_csr_aliasing 4.180s 1.589ms 1 1 100.00
keymgr_same_csr_outstanding 1.890s 319.667us 1 1 100.00
V2 tl_d_partial_access keymgr_csr_hw_reset 0.910s 17.488us 1 1 100.00
keymgr_csr_rw 1.160s 22.107us 1 1 100.00
keymgr_csr_aliasing 4.180s 1.589ms 1 1 100.00
keymgr_same_csr_outstanding 1.890s 319.667us 1 1 100.00
V2 TOTAL 16 16 100.00
V2S sec_cm_additional_check keymgr_sec_cm 8.920s 1.688ms 1 1 100.00
V2S tl_intg_err keymgr_sec_cm 8.920s 1.688ms 1 1 100.00
keymgr_tl_intg_err 1.910s 105.408us 1 1 100.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 2.040s 205.218us 1 1 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 2.040s 205.218us 1 1 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 2.040s 205.218us 1 1 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 2.040s 205.218us 1 1 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 5.330s 1.661ms 1 1 100.00
V2S prim_count_check keymgr_sec_cm 8.920s 1.688ms 1 1 100.00
V2S prim_fsm_check keymgr_sec_cm 8.920s 1.688ms 1 1 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 1.910s 105.408us 1 1 100.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 2.040s 205.218us 1 1 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 2.410s 137.181us 1 1 100.00
V2S sec_cm_reseed_config_regwen keymgr_random 34.220s 9.864ms 1 1 100.00
keymgr_csr_rw 1.160s 22.107us 1 1 100.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 34.220s 9.864ms 1 1 100.00
keymgr_csr_rw 1.160s 22.107us 1 1 100.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 34.220s 9.864ms 1 1 100.00
keymgr_csr_rw 1.160s 22.107us 1 1 100.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 3.070s 153.780us 1 1 100.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 2.100s 76.612us 1 1 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 2.100s 76.612us 1 1 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 34.220s 9.864ms 1 1 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 2.270s 69.923us 1 1 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 8.920s 1.688ms 1 1 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 8.920s 1.688ms 1 1 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 8.920s 1.688ms 1 1 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 4.700s 701.600us 1 1 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 3.070s 153.780us 1 1 100.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 8.920s 1.688ms 1 1 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 8.920s 1.688ms 1 1 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 8.920s 1.688ms 1 1 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 4.700s 701.600us 1 1 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 4.700s 701.600us 1 1 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 8.920s 1.688ms 1 1 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 4.700s 701.600us 1 1 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 8.920s 1.688ms 1 1 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 4.700s 701.600us 1 1 100.00
V2S TOTAL 6 6 100.00
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 5.990s 329.302us 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 30 100.00