| V1 |
smoke |
keymgr_dpe_smoke |
17.810s |
12.019ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
keymgr_dpe_csr_hw_reset |
0.870s |
90.431us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
keymgr_dpe_csr_rw |
0.920s |
46.837us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
keymgr_dpe_csr_bit_bash |
7.670s |
597.116us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
keymgr_dpe_csr_aliasing |
1.910s |
48.284us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
keymgr_dpe_csr_mem_rw_with_rand_reset |
1.220s |
68.703us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
keymgr_dpe_csr_rw |
0.920s |
46.837us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
1.910s |
48.284us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
intr_test |
keymgr_dpe_intr_test |
0.670s |
49.936us |
1 |
1 |
100.00 |
| V2 |
alert_test |
keymgr_dpe_alert_test |
0.720s |
18.204us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
keymgr_dpe_tl_errors |
1.350s |
229.575us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
keymgr_dpe_tl_errors |
1.350s |
229.575us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
keymgr_dpe_csr_hw_reset |
0.870s |
90.431us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
0.920s |
46.837us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
1.910s |
48.284us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
2.330s |
168.839us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
keymgr_dpe_csr_hw_reset |
0.870s |
90.431us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
0.920s |
46.837us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
1.910s |
48.284us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
2.330s |
168.839us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
4 |
4 |
100.00 |
| V2S |
tl_intg_err |
keymgr_dpe_sec_cm |
7.160s |
449.293us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_tl_intg_err |
1.970s |
248.774us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error |
keymgr_dpe_shadow_reg_errors |
1.400s |
147.426us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
keymgr_dpe_shadow_reg_errors |
1.400s |
147.426us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
keymgr_dpe_shadow_reg_errors |
1.400s |
147.426us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
keymgr_dpe_shadow_reg_errors |
1.400s |
147.426us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
keymgr_dpe_shadow_reg_errors_with_csr_rw |
2.230s |
140.953us |
1 |
1 |
100.00 |
| V2S |
prim_count_check |
keymgr_dpe_sec_cm |
7.160s |
449.293us |
1 |
1 |
100.00 |
| V2S |
prim_fsm_check |
keymgr_dpe_sec_cm |
7.160s |
449.293us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
4 |
4 |
100.00 |
|
|
TOTAL |
|
|
14 |
14 |
100.00 |