KMAC/MASKED Simulation Results

Tuesday October 07 2025 16:07:43 UTC

GitHub Revision: 0f6fcf0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	47.190s	6.716ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.150s	30.206us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.070s	31.232us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	9.220s	762.360us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	5.940s	143.959us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.160s	50.333us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.070s	31.232us	1	1	100.00
		kmac_csr_aliasing	5.940s	143.959us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.040s	19.330us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.390s	226.542us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	39.198m	95.465ms	1	1	100.00
V2	burst_write	kmac_burst_write	2.405m	26.183ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	29.680s	9.130ms	1	1	100.00
		kmac_test_vectors_sha3_256	33.579m	130.619ms	1	1	100.00
		kmac_test_vectors_sha3_384	23.436m	46.420ms	1	1	100.00
		kmac_test_vectors_sha3_512	20.090s	12.129ms	1	1	100.00
		kmac_test_vectors_shake_128	3.660m	90.008ms	1	1	100.00
		kmac_test_vectors_shake_256	4.749m	15.810ms	1	1	100.00
		kmac_test_vectors_kmac	2.490s	52.843us	1	1	100.00
		kmac_test_vectors_kmac_xof	1.950s	72.036us	1	1	100.00
V2	sideload	kmac_sideload	4.528m	13.425ms	1	1	100.00
V2	app	kmac_app	1.555m	9.547ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.370m	10.873ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.316m	14.114ms	1	1	100.00
V2	error	kmac_error	3.352m	200.000ms	0	1	0.00
V2	key_error	kmac_key_error	4.610s	692.697us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	1.990s	47.288us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.240s	57.762us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.520s	150.297us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	8.310s	1.774ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	7.350s	486.069us	1	1	100.00
V2	stress_all	kmac_stress_all	1.416m	14.274ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.880s	27.651us	1	1	100.00
V2	alert_test	kmac_alert_test	1.060s	48.174us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	1.950s	178.827us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	1.950s	178.827us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.150s	30.206us	1	1	100.00
		kmac_csr_rw	1.070s	31.232us	1	1	100.00
		kmac_csr_aliasing	5.940s	143.959us	1	1	100.00
		kmac_same_csr_outstanding	1.910s	131.183us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.150s	30.206us	1	1	100.00
		kmac_csr_rw	1.070s	31.232us	1	1	100.00
		kmac_csr_aliasing	5.940s	143.959us	1	1	100.00
		kmac_same_csr_outstanding	1.910s	131.183us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.900s	154.911us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.900s	154.911us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.900s	154.911us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.900s	154.911us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.040s	174.637us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	1.438m	17.139ms	1	1	100.00
		kmac_tl_intg_err	2.980s	118.114us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.980s	118.114us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	7.350s	486.069us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	47.190s	6.716ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	4.528m	13.425ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.900s	154.911us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.438m	17.139ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.438m	17.139ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.438m	17.139ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	47.190s	6.716ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	7.350s	486.069us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.438m	17.139ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.626m	12.630ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	47.190s	6.716ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	42.020s	24.126ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test kmac_error has 1 failures.

    • 0.kmac_error.71408421611446687800669176034754721151715859416502732244313797063482816753468
      Line 179, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_error/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---