OTBN Simulation Results

Tuesday October 07 2025 16:07:43 UTC

GitHub Revision: 0f6fcf0

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 8.000s 183.915us 0 1 0.00
V1 single_binary otbn_single 6.000s 33.790us 0 1 0.00
V1 csr_hw_reset otbn_csr_hw_reset 4.000s 17.771us 1 1 100.00
V1 csr_rw otbn_csr_rw 4.000s 17.325us 1 1 100.00
V1 csr_bit_bash otbn_csr_bit_bash 6.000s 102.020us 1 1 100.00
V1 csr_aliasing otbn_csr_aliasing 4.000s 18.809us 1 1 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 5.000s 271.894us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 4.000s 17.325us 1 1 100.00
otbn_csr_aliasing 4.000s 18.809us 1 1 100.00
V1 mem_walk otbn_mem_walk 20.000s 1.390ms 1 1 100.00
V1 mem_partial_access otbn_mem_partial_access 8.000s 264.384us 1 1 100.00
V1 TOTAL 7 9 77.78
V2 reset_recovery otbn_reset 33.000s 118.805us 0 1 0.00
V2 multi_error otbn_multi_err 51.000s 176.438us 0 1 0.00
V2 back_to_back otbn_multi 57.000s 193.679us 0 1 0.00
V2 stress_all otbn_stress_all 9.000s 30.294us 0 1 0.00
V2 lc_escalation otbn_escalate 5.000s 38.648us 1 1 100.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 7.000s 27.870us 1 1 100.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 12.000s 54.081us 0 1 0.00
V2 alert_test otbn_alert_test 4.000s 28.203us 1 1 100.00
V2 intr_test otbn_intr_test 2.000s 39.810us 1 1 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 6.000s 52.865us 1 1 100.00
V2 tl_d_illegal_access otbn_tl_errors 6.000s 52.865us 1 1 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 4.000s 17.771us 1 1 100.00
otbn_csr_rw 4.000s 17.325us 1 1 100.00
otbn_csr_aliasing 4.000s 18.809us 1 1 100.00
otbn_same_csr_outstanding 3.000s 262.826us 1 1 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 4.000s 17.771us 1 1 100.00
otbn_csr_rw 4.000s 17.325us 1 1 100.00
otbn_csr_aliasing 4.000s 18.809us 1 1 100.00
otbn_same_csr_outstanding 3.000s 262.826us 1 1 100.00
V2 TOTAL 6 11 54.55
V2S mem_integrity otbn_imem_err 7.000s 33.046us 0 1 0.00
otbn_dmem_err 5.003s 0 1 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 8.000s 78.043us 0 1 0.00
otbn_controller_ispr_rdata_err 8.000s 57.923us 0 1 0.00
otbn_mac_bignum_acc_err 9.000s 71.764us 0 1 0.00
otbn_urnd_err 4.000s 10.639us 1 1 100.00
V2S illegal_bus_access otbn_illegal_mem_acc 5.000s 11.799us 0 1 0.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 5.000s 20.196us 1 1 100.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 6.000s 25.717us 1 1 100.00
V2S tl_intg_err otbn_sec_cm 6.000s 23.357us 0 1 0.00
otbn_tl_intg_err 9.000s 63.189us 1 1 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 12.000s 188.797us 1 1 100.00
V2S prim_fsm_check otbn_sec_cm 6.000s 23.357us 0 1 0.00
V2S prim_count_check otbn_sec_cm 6.000s 23.357us 0 1 0.00
V2S sec_cm_mem_scramble otbn_smoke 8.000s 183.915us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 5.003s 0 1 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 7.000s 33.046us 0 1 0.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 9.000s 63.189us 1 1 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 5.000s 38.648us 1 1 100.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 7.000s 33.046us 0 1 0.00
otbn_dmem_err 5.003s 0 1 0.00
otbn_zero_state_err_urnd 7.000s 27.870us 1 1 100.00
otbn_illegal_mem_acc 5.000s 11.799us 0 1 0.00
otbn_sec_cm 6.000s 23.357us 0 1 0.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 6.000s 23.357us 0 1 0.00
V2S sec_cm_scramble_key_sideload otbn_single 6.000s 33.790us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 7.000s 33.046us 0 1 0.00
otbn_dmem_err 5.003s 0 1 0.00
otbn_zero_state_err_urnd 7.000s 27.870us 1 1 100.00
otbn_illegal_mem_acc 5.000s 11.799us 0 1 0.00
otbn_sec_cm 6.000s 23.357us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 6.000s 23.357us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 5.000s 38.648us 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 7.000s 33.046us 0 1 0.00
otbn_dmem_err 5.003s 0 1 0.00
otbn_zero_state_err_urnd 7.000s 27.870us 1 1 100.00
otbn_illegal_mem_acc 5.000s 11.799us 0 1 0.00
otbn_sec_cm 6.000s 23.357us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 6.000s 23.357us 0 1 0.00
V2S sec_cm_data_reg_sw_sca otbn_single 6.000s 33.790us 0 1 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 5.000s 31.864us 0 1 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 5.000s 37.710us 1 1 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 30.000s 143.041us 0 1 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 30.000s 143.041us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 6.000s 32.556us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 6.000s 23.357us 0 1 0.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 6.000s 23.357us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 11.000s 78.922us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 6.000s 23.357us 0 1 0.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 6.000s 23.357us 0 1 0.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 5.000s 47.113us 0 1 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 5.000s 47.113us 0 1 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 4.000s 16.905us 1 1 100.00
V2S sec_cm_data_mem_sec_wipe otbn_single 6.000s 33.790us 0 1 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 6.000s 33.790us 0 1 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 6.000s 33.790us 0 1 0.00
V2S sec_cm_write_mem_integrity otbn_multi 57.000s 193.679us 0 1 0.00
V2S sec_cm_ctrl_flow_count otbn_single 6.000s 33.790us 0 1 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 6.000s 33.790us 0 1 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 6.000s 28.838us 0 1 0.00
V2S sec_cm_key_sideload otbn_single 6.000s 33.790us 0 1 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 6.000s 23.357us 0 1 0.00
V2S TOTAL 7 20 35.00
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 3.567m 1.183ms 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 41 48.78

Failure Buckets