ROM_CTRL/64KB Simulation Results

Tuesday October 07 2025 16:07:43 UTC

GitHub Revision: 0f6fcf0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 7.840s 724.661us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 9.470s 317.044us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 7.320s 315.789us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 8.060s 263.954us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 7.520s 384.437us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 8.070s 580.491us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.320s 315.789us 1 1 100.00
rom_ctrl_csr_aliasing 7.520s 384.437us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.900s 1.109ms 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 7.250s 291.785us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 11.550s 1.851ms 1 1 100.00
V2 stress_all rom_ctrl_stress_all 24.610s 1.604ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 15.330s 712.976us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 6.050s 956.131us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 9.540s 302.800us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 9.540s 302.800us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 9.470s 317.044us 1 1 100.00
rom_ctrl_csr_rw 7.320s 315.789us 1 1 100.00
rom_ctrl_csr_aliasing 7.520s 384.437us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.210s 743.696us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 9.470s 317.044us 1 1 100.00
rom_ctrl_csr_rw 7.320s 315.789us 1 1 100.00
rom_ctrl_csr_aliasing 7.520s 384.437us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.210s 743.696us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.934m 4.316ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 39.620s 1.657ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 7.731m 991.062us 1 1 100.00
rom_ctrl_tl_intg_err 53.230s 299.854us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 7.731m 991.062us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 7.731m 991.062us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.934m 4.316ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.934m 4.316ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.934m 4.316ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.934m 4.316ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.934m 4.316ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 7.731m 991.062us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 7.731m 991.062us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 7.840s 724.661us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 7.840s 724.661us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 7.840s 724.661us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 53.230s 299.854us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.934m 4.316ms 1 1 100.00
rom_ctrl_kmac_err_chk 15.330s 712.976us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.934m 4.316ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.934m 4.316ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.934m 4.316ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 39.620s 1.657ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 7.731m 991.062us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.090m 2.479ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00