0f6fcf0| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 0.970s | 74.683us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.610s | 48.271us | 1 | 1 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.760s | 35.677us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 1.710s | 232.026us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.740s | 17.608us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 0.650s | 43.834us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.760s | 35.677us | 1 | 1 | 100.00 |
| rv_timer_csr_aliasing | 0.740s | 17.608us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 6 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 0.730s | 481.069us | 0 | 1 | 0.00 |
| V2 | disabled | rv_timer_disabled | 1.780s | 2.637ms | 1 | 1 | 100.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 4.363m | 1.033s | 1 | 1 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 4.363m | 1.033s | 1 | 1 | 100.00 |
| V2 | stress | rv_timer_stress_all | 0.960s | 330.816us | 1 | 1 | 100.00 |
| V2 | alert_test | rv_timer_alert_test | 0.640s | 47.221us | 1 | 1 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.650s | 52.122us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 1.220s | 104.680us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 1.220s | 104.680us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.610s | 48.271us | 1 | 1 | 100.00 |
| rv_timer_csr_rw | 0.760s | 35.677us | 1 | 1 | 100.00 | ||
| rv_timer_csr_aliasing | 0.740s | 17.608us | 1 | 1 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.780s | 51.754us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.610s | 48.271us | 1 | 1 | 100.00 |
| rv_timer_csr_rw | 0.760s | 35.677us | 1 | 1 | 100.00 | ||
| rv_timer_csr_aliasing | 0.740s | 17.608us | 1 | 1 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.780s | 51.754us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 7 | 8 | 87.50 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.950s | 61.189us | 1 | 1 | 100.00 |
| rv_timer_tl_intg_err | 0.990s | 140.271us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 0.990s | 140.271us | 1 | 1 | 100.00 |
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| V3 | min_value | rv_timer_min | 1.450s | 742.541us | 0 | 1 | 0.00 |
| V3 | max_value | rv_timer_max | 0.630s | 84.946us | 0 | 1 | 0.00 |
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 30.210s | 3.548ms | 1 | 1 | 100.00 |
| V3 | TOTAL | 1 | 3 | 33.33 | |||
| TOTAL | 16 | 19 | 84.21 |
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:
Test rv_timer_min has 1 failures.
0.rv_timer_min.97260854632487578727366771431916017978936278629537278453529722666408819085881
Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
UVM_FATAL @ 742540643 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x92c39f04) == 0x1
UVM_INFO @ 742540643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_timer_random_reset has 1 failures.
0.rv_timer_random_reset.3481391150779808066655103286373479983453095840744555760031405421031427251770
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 481069344 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x7ffe6504) == 0x1
UVM_INFO @ 481069344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:
0.rv_timer_max.78954692657728031928953480959556220127952776077172595910392357283326300005725
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
UVM_ERROR @ 84946066 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 84946066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---