SPI_HOST Simulation Results

Tuesday October 07 2025 16:07:43 UTC

GitHub Revision: 0f6fcf0

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	48.000s	6.034ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	19.030us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	1.000s	31.490us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	3.000s	318.304us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	61.123us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	1.000s	37.221us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	1.000s	31.490us	1	1	100.00
		spi_host_csr_aliasing	2.000s	61.123us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	1.000s	15.981us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	91.801us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	7.000s	55.837us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	8.000s	259.936us	1	1	100.00
		spi_host_error_cmd	7.000s	61.405us	1	1	100.00
		spi_host_event	12.000s	2.794ms	1	1	100.00
V2	clock_rate	spi_host_speed	10.000s	114.853us	1	1	100.00
V2	speed	spi_host_speed	10.000s	114.853us	1	1	100.00
V2	chip_select_timing	spi_host_speed	10.000s	114.853us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	8.000s	65.088us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	7.000s	26.836us	1	1	100.00
V2	cpol_cpha	spi_host_speed	10.000s	114.853us	1	1	100.00
V2	full_cycle	spi_host_speed	10.000s	114.853us	1	1	100.00
V2	duplex	spi_host_smoke	48.000s	6.034ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	48.000s	6.034ms	1	1	100.00
V2	stress_all	spi_host_stress_all	5.000s	366.950us	1	1	100.00
V2	spien	spi_host_spien	5.000s	2.928ms	1	1	100.00
V2	stall	spi_host_status_stall	25.000s	4.267ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	5.000s	202.203us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	8.000s	259.936us	1	1	100.00
V2	alert_test	spi_host_alert_test	1.000s	19.870us	1	1	100.00
V2	intr_test	spi_host_intr_test	1.000s	22.014us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	3.000s	210.258us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	3.000s	210.258us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	19.030us	1	1	100.00
		spi_host_csr_rw	1.000s	31.490us	1	1	100.00
		spi_host_csr_aliasing	2.000s	61.123us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	122.073us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	19.030us	1	1	100.00
		spi_host_csr_rw	1.000s	31.490us	1	1	100.00
		spi_host_csr_aliasing	2.000s	61.123us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	122.073us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	1.000s	49.324us	1	1	100.00
		spi_host_sec_cm	1.000s	434.402us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	1.000s	49.324us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	6.917m	13.105ms	1	1	100.00
		TOTAL			26	26	100.00