SRAM_CTRL/MAIN Simulation Results

Tuesday October 07 2025 16:07:43 UTC

GitHub Revision: 0f6fcf0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	10.730s	426.020us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.000s	23.000us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.790s	40.853us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.600s	120.289us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.000s	231.785us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.400s	369.827us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.790s	40.853us	1	1	100.00
		sram_ctrl_csr_aliasing	1.000s	231.785us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	2.219m	64.610ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	56.370s	3.092ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	3.850m	58.572ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	4.807m	5.518ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	10.369m	110.282ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	9.544m	11.029ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	38.600s	22.729ms	1	1	100.00
V2	executable	sram_ctrl_executable	8.839m	39.712ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	16.170s	1.261ms	1	1	100.00
		sram_ctrl_partial_access_b2b	5.685m	76.020ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	24.430s	802.249us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	3.570s	670.559us	1	1	100.00
		sram_ctrl_throughput_w_readback	59.140s	1.550ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	12.300m	96.071ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.400s	693.807us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	30.926m	42.252ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.880s	12.878us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.850s	149.976us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.850s	149.976us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.000s	23.000us	1	1	100.00
		sram_ctrl_csr_rw	0.790s	40.853us	1	1	100.00
		sram_ctrl_csr_aliasing	1.000s	231.785us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.870s	47.732us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.000s	23.000us	1	1	100.00
		sram_ctrl_csr_rw	0.790s	40.853us	1	1	100.00
		sram_ctrl_csr_aliasing	1.000s	231.785us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.870s	47.732us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	16.160s	3.728ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.690s	17.995us	0	1	0.00
		sram_ctrl_tl_intg_err	1.780s	198.879us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.690s	17.995us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.780s	198.879us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	12.300m	96.071ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	12.300m	96.071ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.790s	40.853us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	8.839m	39.712ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	8.839m	39.712ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	8.839m	39.712ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	38.600s	22.729ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	6.010s	8.289ms	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	16.160s	3.728ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.240s	1.332ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	10.730s	426.020us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	10.730s	426.020us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	8.839m	39.712ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.690s	17.995us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	38.600s	22.729ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.690s	17.995us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.690s	17.995us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	10.730s	426.020us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.690s	17.995us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	44.890s	16.535ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.111317239163198469706418282280595545066043856275375266674818227522613385624552
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 8288504913 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 8288504913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.29109823851770579881846287935046245709618917226060782696776404454127687309681
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  17995191 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  17995191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---