UART Simulation Results

Tuesday October 07 2025 16:07:43 UTC

GitHub Revision: 0f6fcf0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.270s	317.936us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.820s	24.813us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.620s	20.106us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.250s	1.241ms	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.710s	16.210us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.670s	60.244us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.620s	20.106us	1	1	100.00
		uart_csr_aliasing	0.710s	16.210us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	44.400s	140.642ms	1	1	100.00
V2	parity	uart_smoke	1.270s	317.936us	1	1	100.00
		uart_tx_rx	44.400s	140.642ms	1	1	100.00
V2	parity_error	uart_intr	12.450s	23.761ms	1	1	100.00
		uart_rx_parity_err	22.390s	47.499ms	1	1	100.00
V2	watermark	uart_tx_rx	44.400s	140.642ms	1	1	100.00
		uart_intr	12.450s	23.761ms	1	1	100.00
V2	fifo_full	uart_fifo_full	2.153m	119.952ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	14.960s	45.273ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	20.900s	67.100ms	1	1	100.00
V2	rx_frame_err	uart_intr	12.450s	23.761ms	1	1	100.00
V2	rx_break_err	uart_intr	12.450s	23.761ms	1	1	100.00
V2	rx_timeout	uart_intr	12.450s	23.761ms	1	1	100.00
V2	perf	uart_perf	3.759m	10.640ms	1	1	100.00
V2	sys_loopback	uart_loopback	8.410s	6.359ms	1	1	100.00
V2	line_loopback	uart_loopback	8.410s	6.359ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	3.010s	2.864ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	5.310s	3.466ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	6.930s	7.548ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	26.330s	4.568ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	12.273m	188.452ms	1	1	100.00
V2	stress_all	uart_stress_all	38.140s	106.058ms	1	1	100.00
V2	alert_test	uart_alert_test	0.560s	17.028us	1	1	100.00
V2	intr_test	uart_intr_test	0.770s	13.539us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.610s	96.800us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.610s	96.800us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.820s	24.813us	1	1	100.00
		uart_csr_rw	0.620s	20.106us	1	1	100.00
		uart_csr_aliasing	0.710s	16.210us	1	1	100.00
		uart_same_csr_outstanding	0.610s	13.940us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.820s	24.813us	1	1	100.00
		uart_csr_rw	0.620s	20.106us	1	1	100.00
		uart_csr_aliasing	0.710s	16.210us	1	1	100.00
		uart_same_csr_outstanding	0.610s	13.940us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	0.760s	175.524us	1	1	100.00
		uart_tl_intg_err	1.290s	303.925us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.290s	303.925us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	13.080s	3.490ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.55169545265557241843662812865364083928525172383205849198763260307362066826619
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 424088999 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 424088999 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 424088999 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 537808999 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 4,                                 clk_pulses: 0
        UVM_ERROR @ 537848999 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (166 [0xa6] vs 255 [0xff]) reg name: uart_reg_block.rdata