DMA Simulation Results

Wednesday October 08 2025 16:07:13 UTC

GitHub Revision: e4ce7cf

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	4.000s	231.597us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	5.000s	299.296us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	6.000s	348.614us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	1.000s	28.597us	1	1	100.00
V1	csr_rw	dma_csr_rw	2.000s	76.015us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	6.000s	522.610us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	6.000s	1.735ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	1.000s	102.035us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	2.000s	76.015us	1	1	100.00
		dma_csr_aliasing	6.000s	1.735ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.333m	17.394ms	1	1	100.00
V2	dma_memory_tl_error	dma_memory_stress	1.183m	6.970ms	1	1	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	18.317m	185.478ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	18.317m	185.478ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	1.183m	6.970ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	11.900m	290.818ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	18.317m	185.478ms	1	1	100.00
V2	dma_abort	dma_abort	11.000s	802.625us	1	1	100.00
V2	dma_stress_all	dma_stress_all	3.467m	41.772ms	1	1	100.00
V2	alert_test	dma_alert_test	2.000s	14.575us	1	1	100.00
V2	intr_test	dma_intr_test	1.000s	13.153us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	3.000s	159.288us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	3.000s	159.288us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	1.000s	28.597us	1	1	100.00
		dma_csr_rw	2.000s	76.015us	1	1	100.00
		dma_csr_aliasing	6.000s	1.735ms	1	1	100.00
		dma_same_csr_outstanding	2.000s	51.573us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	1.000s	28.597us	1	1	100.00
		dma_csr_rw	2.000s	76.015us	1	1	100.00
		dma_csr_aliasing	6.000s	1.735ms	1	1	100.00
		dma_same_csr_outstanding	2.000s	51.573us	1	1	100.00
V2		TOTAL			10	10	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	9.000s	379.433us	1	1	100.00
		dma_generic_stress	11.900m	290.818ms	1	1	100.00
		dma_handshake_stress	18.317m	185.478ms	1	1	100.00
V2S	dma_config_lock	dma_config_lock	9.000s	633.960us	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	4.000s	237.239us	1	1	100.00
		dma_sec_cm	2.000s	45.867us	1	1	100.00
V2S		TOTAL			4	4	100.00
	Unmapped tests	dma_short_transfer	2.017m	11.459ms	1	1	100.00
		dma_longer_transfer	3.000s	587.460us	1	1	100.00
		dma_stress_all_with_rand_reset	5.000s	336.906us	0	1	0.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.114251047259762489456720617963212358678328164423192158306235162398581792887655
      Line 88, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  336906238ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @  336906238ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---