EDN Simulation Results

Wednesday October 08 2025 16:07:13 UTC

GitHub Revision: e4ce7cf

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.890s	29.305us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.800s	46.414us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.760s	13.796us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	2.470s	202.657us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.080s	64.759us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	0.880s	37.874us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.760s	13.796us	1	1	100.00
		edn_csr_aliasing	1.080s	64.759us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.030s	51.837us	1	1	100.00
V2	csrng_commands	edn_genbits	1.030s	51.837us	1	1	100.00
V2	genbits	edn_genbits	1.030s	51.837us	1	1	100.00
V2	interrupts	edn_intr	0.820s	33.584us	1	1	100.00
V2	alerts	edn_alert	0.970s	51.755us	1	1	100.00
V2	errs	edn_err	1.050s	45.961us	1	1	100.00
V2	disable	edn_disable	0.820s	12.681us	1	1	100.00
		edn_disable_auto_req_mode	0.960s	35.509us	1	1	100.00
V2	stress_all	edn_stress_all	3.760s	575.454us	1	1	100.00
V2	intr_test	edn_intr_test	0.810s	12.692us	1	1	100.00
V2	alert_test	edn_alert_test	0.780s	48.433us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.830s	123.554us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.830s	123.554us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.800s	46.414us	1	1	100.00
		edn_csr_rw	0.760s	13.796us	1	1	100.00
		edn_csr_aliasing	1.080s	64.759us	1	1	100.00
		edn_same_csr_outstanding	1.080s	32.994us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.800s	46.414us	1	1	100.00
		edn_csr_rw	0.760s	13.796us	1	1	100.00
		edn_csr_aliasing	1.080s	64.759us	1	1	100.00
		edn_same_csr_outstanding	1.080s	32.994us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	6.160s	1.188ms	1	1	100.00
		edn_tl_intg_err	1.450s	51.577us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.780s	43.073us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	0.970s	51.755us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.160s	1.188ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.160s	1.188ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	6.160s	1.188ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.160s	1.188ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	0.970s	51.755us	1	1	100.00
		edn_sec_cm	6.160s	1.188ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	0.970s	51.755us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	1.450s	51.577us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	23.240s	1.416ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00