HMAC Simulation Results

Wednesday October 08 2025 16:07:13 UTC

GitHub Revision: e4ce7cf

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 8.210s 2.675ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.900s 42.433us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.790s 28.143us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 3.970s 2.735ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 5.670s 1.016ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 0.820s 28.773us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.790s 28.143us 1 1 100.00
hmac_csr_aliasing 5.670s 1.016ms 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 1.015m 6.568ms 1 1 100.00
V2 back_pressure hmac_back_pressure 29.350s 4.923ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 7.540s 167.305us 1 1 100.00
hmac_test_sha384_vectors 6.496m 50.345ms 1 1 100.00
hmac_test_sha512_vectors 18.530s 226.739us 1 1 100.00
hmac_test_hmac256_vectors 7.540s 274.476us 1 1 100.00
hmac_test_hmac384_vectors 8.660s 829.203us 1 1 100.00
hmac_test_hmac512_vectors 9.100s 585.911us 1 1 100.00
V2 burst_wr hmac_burst_wr 17.310s 6.173ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 5.941m 14.986ms 1 1 100.00
V2 error hmac_error 16.160s 3.906ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.235m 71.402ms 1 1 100.00
V2 save_and_restore hmac_smoke 8.210s 2.675ms 1 1 100.00
hmac_long_msg 1.015m 6.568ms 1 1 100.00
hmac_back_pressure 29.350s 4.923ms 1 1 100.00
hmac_datapath_stress 5.941m 14.986ms 1 1 100.00
hmac_burst_wr 17.310s 6.173ms 1 1 100.00
hmac_stress_all 1.401m 29.852ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 8.210s 2.675ms 1 1 100.00
hmac_long_msg 1.015m 6.568ms 1 1 100.00
hmac_back_pressure 29.350s 4.923ms 1 1 100.00
hmac_datapath_stress 5.941m 14.986ms 1 1 100.00
hmac_wipe_secret 1.235m 71.402ms 1 1 100.00
hmac_test_sha256_vectors 7.540s 167.305us 1 1 100.00
hmac_test_sha384_vectors 6.496m 50.345ms 1 1 100.00
hmac_test_sha512_vectors 18.530s 226.739us 1 1 100.00
hmac_test_hmac256_vectors 7.540s 274.476us 1 1 100.00
hmac_test_hmac384_vectors 8.660s 829.203us 1 1 100.00
hmac_test_hmac512_vectors 9.100s 585.911us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 8.210s 2.675ms 1 1 100.00
hmac_long_msg 1.015m 6.568ms 1 1 100.00
hmac_back_pressure 29.350s 4.923ms 1 1 100.00
hmac_datapath_stress 5.941m 14.986ms 1 1 100.00
hmac_burst_wr 17.310s 6.173ms 1 1 100.00
hmac_error 16.160s 3.906ms 1 1 100.00
hmac_wipe_secret 1.235m 71.402ms 1 1 100.00
hmac_test_sha256_vectors 7.540s 167.305us 1 1 100.00
hmac_test_sha384_vectors 6.496m 50.345ms 1 1 100.00
hmac_test_sha512_vectors 18.530s 226.739us 1 1 100.00
hmac_test_hmac256_vectors 7.540s 274.476us 1 1 100.00
hmac_test_hmac384_vectors 8.660s 829.203us 1 1 100.00
hmac_test_hmac512_vectors 9.100s 585.911us 1 1 100.00
hmac_stress_all 1.401m 29.852ms 1 1 100.00
V2 stress_all hmac_stress_all 1.401m 29.852ms 1 1 100.00
V2 alert_test hmac_alert_test 0.670s 10.619us 1 1 100.00
V2 intr_test hmac_intr_test 0.710s 73.450us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 1.740s 107.562us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 1.740s 107.562us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.900s 42.433us 1 1 100.00
hmac_csr_rw 0.790s 28.143us 1 1 100.00
hmac_csr_aliasing 5.670s 1.016ms 1 1 100.00
hmac_same_csr_outstanding 0.910s 26.985us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.900s 42.433us 1 1 100.00
hmac_csr_rw 0.790s 28.143us 1 1 100.00
hmac_csr_aliasing 5.670s 1.016ms 1 1 100.00
hmac_same_csr_outstanding 0.910s 26.985us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.990s 253.074us 1 1 100.00
hmac_tl_intg_err 1.510s 159.474us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 1.510s 159.474us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 8.210s 2.675ms 1 1 100.00
V3 stress_reset hmac_stress_reset 1.710s 342.067us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.631m 15.226ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 3.430s 247.278us 1 1 100.00
TOTAL 28 28 100.00