I2C Simulation Results

Wednesday October 08 2025 16:07:13 UTC

GitHub Revision: e4ce7cf

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	11.890s	4.139ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	19.620s	808.881us	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.660s	17.460us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.850s	20.332us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	1.890s	228.452us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.050s	54.373us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.890s	25.463us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.850s	20.332us	1	1	100.00
		i2c_csr_aliasing	1.050s	54.373us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	3.330s	351.404us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	7.883m	61.585ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	3.978m	13.007ms	1	1	100.00
V2	host_override	i2c_host_override	0.680s	25.965us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	49.320s	3.700ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	53.190s	2.808ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.050s	1.421ms	1	1	100.00
		i2c_host_fifo_fmt_empty	14.790s	433.518us	1	1	100.00
		i2c_host_fifo_reset_rx	2.600s	151.028us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.288m	3.977ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	25.380s	1.720ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	0.860s	119.197us	0	1	0.00
V2	target_glitch	i2c_target_glitch	1.830s	507.352us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	1.135m	75.684ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.670s	1.937ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	10.740s	772.633us	1	1	100.00
		i2c_target_intr_smoke	5.690s	2.430ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.480s	498.176us	1	1	100.00
		i2c_target_fifo_reset_tx	1.520s	181.660us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	14.480s	10.617ms	1	1	100.00
		i2c_target_stress_rd	10.740s	772.633us	1	1	100.00
		i2c_target_intr_stress_wr	5.390s	7.182ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.030s	1.360ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	1.970s	820.123us	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.870s	1.337ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	1.640s	815.921us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.730s	1.838ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.270s	576.558us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	3.978m	13.007ms	1	1	100.00
		i2c_host_perf_precise	1.010s	48.478us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	25.380s	1.720ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	4.470s	408.052us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.640s	452.786us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.340s	581.560us	1	1	100.00
		i2c_target_nack_txstretch	1.820s	156.375us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	9.930s	364.348us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.730s	8.794ms	1	1	100.00
V2	alert_test	i2c_alert_test	0.630s	36.610us	1	1	100.00
V2	intr_test	i2c_intr_test	0.820s	81.833us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.780s	134.086us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.780s	134.086us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.660s	17.460us	1	1	100.00
		i2c_csr_rw	0.850s	20.332us	1	1	100.00
		i2c_csr_aliasing	1.050s	54.373us	1	1	100.00
		i2c_same_csr_outstanding	0.790s	29.731us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.660s	17.460us	1	1	100.00
		i2c_csr_rw	0.850s	20.332us	1	1	100.00
		i2c_csr_aliasing	1.050s	54.373us	1	1	100.00
		i2c_same_csr_outstanding	0.790s	29.731us	1	1	100.00
V2		TOTAL			34	38	89.47
V2S	tl_intg_err	i2c_tl_intg_err	1.790s	90.402us	1	1	100.00
		i2c_sec_cm	0.940s	166.941us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.790s	90.402us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	9.230s	822.259us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.030s	127.691us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	1.850s	1.536ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			43	50	86.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 2 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.47877360233071809456897877265692113098809559164843519695477983826314757993118
      Line 115, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @ 351403538 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 351403538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.107868645193870660799157508157137041250310923767848287682156583129929622420847
      Line 135, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 61584852305 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 61584852305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.37762848754411100509016881873541715234477444146728125144026811735738683631650
      Line 88, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 822259421 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 822259421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.99092556853064380915407830835036782826022702655108591409996636641227369287427
      Line 80, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1536054213 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1536054213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.19954303969676158389605487053536107408548377742334016470441372765741691768188
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 507352133 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 507352133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.102436468506599499048284582017812651794673252049674516372145304280018924566459
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 127691019 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 151 [0x97])
        UVM_INFO @ 127691019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.4077068629967165547264283772391079222789266533884724197967613001244029852351
      Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @ 119196643 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
        --> EXP:
        ---------------------------------------------------
        Name            Type                Size  Value
        ---------------------------------------------------