| V1 |
smoke |
keymgr_dpe_smoke |
20.040s |
6.127ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
keymgr_dpe_csr_hw_reset |
0.870s |
118.125us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
keymgr_dpe_csr_rw |
1.190s |
93.981us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
keymgr_dpe_csr_bit_bash |
5.450s |
738.264us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
keymgr_dpe_csr_aliasing |
7.290s |
290.765us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
keymgr_dpe_csr_mem_rw_with_rand_reset |
1.710s |
33.429us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
keymgr_dpe_csr_rw |
1.190s |
93.981us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
7.290s |
290.765us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
intr_test |
keymgr_dpe_intr_test |
0.810s |
8.052us |
1 |
1 |
100.00 |
| V2 |
alert_test |
keymgr_dpe_alert_test |
0.770s |
12.741us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
keymgr_dpe_tl_errors |
1.950s |
79.120us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
keymgr_dpe_tl_errors |
1.950s |
79.120us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
keymgr_dpe_csr_hw_reset |
0.870s |
118.125us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
1.190s |
93.981us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
7.290s |
290.765us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
1.680s |
47.933us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
keymgr_dpe_csr_hw_reset |
0.870s |
118.125us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
1.190s |
93.981us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
7.290s |
290.765us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
1.680s |
47.933us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
4 |
4 |
100.00 |
| V2S |
tl_intg_err |
keymgr_dpe_sec_cm |
6.900s |
506.675us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_tl_intg_err |
2.790s |
185.821us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error |
keymgr_dpe_shadow_reg_errors |
1.550s |
213.017us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
keymgr_dpe_shadow_reg_errors |
1.550s |
213.017us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
keymgr_dpe_shadow_reg_errors |
1.550s |
213.017us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
keymgr_dpe_shadow_reg_errors |
1.550s |
213.017us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
keymgr_dpe_shadow_reg_errors_with_csr_rw |
1.980s |
188.775us |
1 |
1 |
100.00 |
| V2S |
prim_count_check |
keymgr_dpe_sec_cm |
6.900s |
506.675us |
1 |
1 |
100.00 |
| V2S |
prim_fsm_check |
keymgr_dpe_sec_cm |
6.900s |
506.675us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
4 |
4 |
100.00 |
|
|
TOTAL |
|
|
14 |
14 |
100.00 |