KMAC/MASKED Simulation Results

Wednesday October 08 2025 16:07:13 UTC

GitHub Revision: e4ce7cf

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	31.840s	4.331ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.940s	121.834us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.120s	31.442us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.130s	387.316us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.590s	1.276ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.770s	36.861us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.120s	31.442us	1	1	100.00
		kmac_csr_aliasing	3.590s	1.276ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.760s	11.777us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.240s	109.887us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	38.413m	110.333ms	1	1	100.00
V2	burst_write	kmac_burst_write	8.103m	6.529ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	29.776m	250.012ms	1	1	100.00
		kmac_test_vectors_sha3_256	33.483m	961.439ms	1	1	100.00
		kmac_test_vectors_sha3_384	22.139m	177.018ms	1	1	100.00
		kmac_test_vectors_sha3_512	13.853m	9.818ms	1	1	100.00
		kmac_test_vectors_shake_128	30.093m	97.406ms	1	1	100.00
		kmac_test_vectors_shake_256	4.527m	43.973ms	1	1	100.00
		kmac_test_vectors_kmac	2.090s	106.746us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.000s	620.239us	1	1	100.00
V2	sideload	kmac_sideload	2.897m	7.554ms	1	1	100.00
V2	app	kmac_app	3.355m	11.937ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.490m	6.292ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.262m	4.620ms	1	1	100.00
V2	error	kmac_error	6.071m	36.067ms	1	1	100.00
V2	key_error	kmac_key_error	13.510s	3.361ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.170s	142.906us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	27.100s	5.070ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.380s	116.367us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	38.260s	14.438ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.780s	199.497us	1	1	100.00
V2	stress_all	kmac_stress_all	12.892m	28.434ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.750s	14.938us	1	1	100.00
V2	alert_test	kmac_alert_test	1.150s	52.288us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	1.760s	78.090us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	1.760s	78.090us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.940s	121.834us	1	1	100.00
		kmac_csr_rw	1.120s	31.442us	1	1	100.00
		kmac_csr_aliasing	3.590s	1.276ms	1	1	100.00
		kmac_same_csr_outstanding	2.010s	184.103us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.940s	121.834us	1	1	100.00
		kmac_csr_rw	1.120s	31.442us	1	1	100.00
		kmac_csr_aliasing	3.590s	1.276ms	1	1	100.00
		kmac_same_csr_outstanding	2.010s	184.103us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.300s	24.306us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.300s	24.306us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.300s	24.306us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.300s	24.306us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.470s	518.971us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	42.860s	3.567ms	1	1	100.00
		kmac_tl_intg_err	1.830s	109.377us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.830s	109.377us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.780s	199.497us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	31.840s	4.331ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	2.897m	7.554ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.300s	24.306us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	42.860s	3.567ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	42.860s	3.567ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	42.860s	3.567ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	31.840s	4.331ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.780s	199.497us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	42.860s	3.567ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.293m	15.067ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	31.840s	4.331ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	59.010s	2.491ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.96693089860469016195947774379481400559833655316962994516519094961505162171010
      Line 375, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2490660813 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 2490660813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---