| V1 |
smoke |
kmac_smoke |
22.810s |
1.313ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
kmac_csr_hw_reset |
0.890s |
52.533us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
kmac_csr_rw |
1.000s |
39.075us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
kmac_csr_bit_bash |
10.120s |
375.377us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
kmac_csr_aliasing |
5.400s |
148.660us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
kmac_csr_mem_rw_with_rand_reset |
1.750s |
36.124us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
kmac_csr_rw |
1.000s |
39.075us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
5.400s |
148.660us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
kmac_mem_walk |
0.670s |
12.853us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
kmac_mem_partial_access |
1.220s |
153.096us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
long_msg_and_output |
kmac_long_msg_and_output |
31.957m |
50.245ms |
1 |
1 |
100.00 |
| V2 |
burst_write |
kmac_burst_write |
11.492m |
91.044ms |
1 |
1 |
100.00 |
| V2 |
test_vectors |
kmac_test_vectors_sha3_224 |
28.780s |
2.355ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_256 |
18.213m |
16.336ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_384 |
17.820s |
1.827ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_512 |
9.369m |
35.044ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_128 |
2.064m |
26.584ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_256 |
1.451m |
9.769ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac |
2.120s |
67.338us |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac_xof |
2.420s |
111.562us |
1 |
1 |
100.00 |
| V2 |
sideload |
kmac_sideload |
5.251m |
40.107ms |
1 |
1 |
100.00 |
| V2 |
app |
kmac_app |
2.793m |
17.120ms |
1 |
1 |
100.00 |
| V2 |
app_with_partial_data |
kmac_app_with_partial_data |
2.115m |
16.734ms |
1 |
1 |
100.00 |
| V2 |
entropy_refresh |
kmac_entropy_refresh |
2.230m |
3.952ms |
1 |
1 |
100.00 |
| V2 |
error |
kmac_error |
3.044m |
22.267ms |
1 |
1 |
100.00 |
| V2 |
key_error |
kmac_key_error |
8.570s |
7.705ms |
1 |
1 |
100.00 |
| V2 |
sideload_invalid |
kmac_sideload_invalid |
1.740s |
71.883us |
1 |
1 |
100.00 |
| V2 |
edn_timeout_error |
kmac_edn_timeout_error |
11.980s |
2.573ms |
1 |
1 |
100.00 |
| V2 |
entropy_mode_error |
kmac_entropy_mode_error |
25.420s |
5.188ms |
1 |
1 |
100.00 |
| V2 |
entropy_ready_error |
kmac_entropy_ready_error |
4.940s |
638.656us |
1 |
1 |
100.00 |
| V2 |
lc_escalation |
kmac_lc_escalation |
5.580s |
447.488us |
1 |
1 |
100.00 |
| V2 |
stress_all |
kmac_stress_all |
56.870s |
3.270ms |
1 |
1 |
100.00 |
| V2 |
intr_test |
kmac_intr_test |
0.710s |
42.945us |
1 |
1 |
100.00 |
| V2 |
alert_test |
kmac_alert_test |
0.930s |
55.044us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
kmac_tl_errors |
1.550s |
128.839us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
kmac_tl_errors |
1.550s |
128.839us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
kmac_csr_hw_reset |
0.890s |
52.533us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
1.000s |
39.075us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
5.400s |
148.660us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
1.290s |
106.102us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
kmac_csr_hw_reset |
0.890s |
52.533us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
1.000s |
39.075us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
5.400s |
148.660us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
1.290s |
106.102us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
26 |
26 |
100.00 |
| V2S |
shadow_reg_update_error |
kmac_shadow_reg_errors |
1.180s |
509.726us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
kmac_shadow_reg_errors |
1.180s |
509.726us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
kmac_shadow_reg_errors |
1.180s |
509.726us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
kmac_shadow_reg_errors |
1.180s |
509.726us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
kmac_shadow_reg_errors_with_csr_rw |
1.780s |
85.193us |
1 |
1 |
100.00 |
| V2S |
tl_intg_err |
kmac_sec_cm |
18.190s |
3.215ms |
1 |
1 |
100.00 |
|
|
kmac_tl_intg_err |
2.940s |
348.034us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
kmac_tl_intg_err |
2.940s |
348.034us |
1 |
1 |
100.00 |
| V2S |
sec_cm_lc_escalate_en_intersig_mubi |
kmac_lc_escalation |
5.580s |
447.488us |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_key_key_masking |
kmac_smoke |
22.810s |
1.313ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_key_sideload |
kmac_sideload |
5.251m |
40.107ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_shadow |
kmac_shadow_reg_errors |
1.180s |
509.726us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_sparse |
kmac_sec_cm |
18.190s |
3.215ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_ctr_redun |
kmac_sec_cm |
18.190s |
3.215ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_packer_ctr_redun |
kmac_sec_cm |
18.190s |
3.215ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_regwen |
kmac_smoke |
22.810s |
1.313ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_global_esc |
kmac_lc_escalation |
5.580s |
447.488us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_local_esc |
kmac_sec_cm |
18.190s |
3.215ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_absorbed_ctrl_mubi |
kmac_mubi |
3.629m |
15.308ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_cmd_ctrl_sparse |
kmac_smoke |
22.810s |
1.313ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
5 |
5 |
100.00 |
| V3 |
stress_all_with_rand_reset |
kmac_stress_all_with_rand_reset |
3.115m |
8.823ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
40 |
40 |
100.00 |