MBX Simulation Results

Wednesday October 08 2025 16:07:13 UTC

GitHub Revision: e4ce7cf

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	mbx_smoke	mbx_smoke	1.267m	21.700ms	1	1	100.00
V1	csr_hw_reset	mbx_csr_hw_reset	1.000s	84.362us	1	1	100.00
V1	csr_rw	mbx_csr_rw	1.000s	24.469us	1	1	100.00
V1	csr_bit_bash	mbx_csr_bit_bash	3.000s	238.628us	1	1	100.00
V1	csr_aliasing	mbx_csr_aliasing	1.000s	91.396us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	mbx_csr_mem_rw_with_rand_reset	2.000s	38.026us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	mbx_csr_rw	1.000s	24.469us	1	1	100.00
		mbx_csr_aliasing	1.000s	91.396us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	mbx_stress	mbx_stress	40.000s	10.690ms	0	1	0.00
V2	mbx_max_activity	mbx_stress_zero_delays	11.000s	371.991us	0	1	0.00
V2	mbx_imbx_oob	mbx_imbx_oob	38.000s	3.303ms	1	1	100.00
V2	mbx_doe_intr_msg	mbx_doe_intr_msg	15.000s	1.490ms	1	1	100.00
V2	alert_test	mbx_alert_test	8.000s	213.084us	1	1	100.00
V2	intr_test	mbx_intr_test	4.000s	78.880us	1	1	100.00
V2	tl_d_oob_addr_access	mbx_tl_errors	9.000s	43.549us	1	1	100.00
V2	tl_d_illegal_access	mbx_tl_errors	9.000s	43.549us	1	1	100.00
V2	tl_d_outstanding_access	mbx_csr_hw_reset	1.000s	84.362us	1	1	100.00
		mbx_csr_rw	1.000s	24.469us	1	1	100.00
		mbx_csr_aliasing	1.000s	91.396us	1	1	100.00
		mbx_same_csr_outstanding	2.000s	95.655us	1	1	100.00
V2	tl_d_partial_access	mbx_csr_hw_reset	1.000s	84.362us	1	1	100.00
		mbx_csr_rw	1.000s	24.469us	1	1	100.00
		mbx_csr_aliasing	1.000s	91.396us	1	1	100.00
		mbx_same_csr_outstanding	2.000s	95.655us	1	1	100.00
V2		TOTAL			6	8	75.00
V2S	tl_intg_err	mbx_tl_intg_err	7.000s	131.738us	1	1	100.00
		mbx_sec_cm	8.000s	29.915us	1	1	100.00
V2S		TOTAL			2	2	100.00
		TOTAL			14	16	87.50

Failure Buckets

• UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register has 1 failures:

  • Test mbx_stress has 1 failures.

    • 0.mbx_stress.58430104160613685113965697489415605473371799191105315378748869117761122361617
      Line 1341, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress/latest/run.log

        UVM_ERROR @ 10689965750 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
        UVM_INFO @ 10689965750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched has 1 failures:

  • Test mbx_stress_zero_delays has 1 failures.

    • 0.mbx_stress_zero_delays.21570493777093626709590725974284898620686899932254112372491047234026708265334
      Line 146, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress_zero_delays/latest/run.log

        UVM_ERROR @ 371991468 ps: (mbx_scoreboard.sv:500) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 3780796545 [0xe15a6081]) RDATA read data mismatched
        UVM_INFO @ 371991468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---