OTBN Simulation Results

Wednesday October 08 2025 16:07:13 UTC

GitHub Revision: e4ce7cf

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 9.000s 138.878us 0 1 0.00
V1 single_binary otbn_single 5.000s 71.727us 0 1 0.00
V1 csr_hw_reset otbn_csr_hw_reset 3.000s 38.318us 1 1 100.00
V1 csr_rw otbn_csr_rw 3.000s 34.958us 1 1 100.00
V1 csr_bit_bash otbn_csr_bit_bash 4.000s 64.398us 1 1 100.00
V1 csr_aliasing otbn_csr_aliasing 4.000s 21.136us 1 1 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 4.000s 63.436us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 3.000s 34.958us 1 1 100.00
otbn_csr_aliasing 4.000s 21.136us 1 1 100.00
V1 mem_walk otbn_mem_walk 21.000s 2.394ms 1 1 100.00
V1 mem_partial_access otbn_mem_partial_access 11.000s 123.600us 1 1 100.00
V1 TOTAL 7 9 77.78
V2 reset_recovery otbn_reset 4.397s 0 1 0.00
V2 multi_error otbn_multi_err 40.000s 348.698us 0 1 0.00
V2 back_to_back otbn_multi 32.000s 309.010us 0 1 0.00
V2 stress_all otbn_stress_all 36.000s 557.550us 0 1 0.00
V2 lc_escalation otbn_escalate 7.000s 65.008us 0 1 0.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 7.000s 33.622us 0 1 0.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 6.000s 129.427us 0 1 0.00
V2 alert_test otbn_alert_test 3.000s 166.336us 1 1 100.00
V2 intr_test otbn_intr_test 3.000s 98.531us 1 1 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 6.000s 735.132us 1 1 100.00
V2 tl_d_illegal_access otbn_tl_errors 6.000s 735.132us 1 1 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 3.000s 38.318us 1 1 100.00
otbn_csr_rw 3.000s 34.958us 1 1 100.00
otbn_csr_aliasing 4.000s 21.136us 1 1 100.00
otbn_same_csr_outstanding 4.000s 33.908us 1 1 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 3.000s 38.318us 1 1 100.00
otbn_csr_rw 3.000s 34.958us 1 1 100.00
otbn_csr_aliasing 4.000s 21.136us 1 1 100.00
otbn_same_csr_outstanding 4.000s 33.908us 1 1 100.00
V2 TOTAL 4 11 36.36
V2S mem_integrity otbn_imem_err 7.000s 18.193us 0 1 0.00
otbn_dmem_err 6.000s 118.632us 0 1 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 6.000s 54.162us 0 1 0.00
otbn_controller_ispr_rdata_err 5.000s 221.460us 0 1 0.00
otbn_mac_bignum_acc_err 12.000s 54.142us 0 1 0.00
otbn_urnd_err 7.000s 22.880us 0 1 0.00
V2S illegal_bus_access otbn_illegal_mem_acc 5.000s 14.391us 1 1 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 8.000s 33.261us 1 1 100.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 5.000s 40.744us 1 1 100.00
V2S tl_intg_err otbn_sec_cm 15.000s 159.456us 0 1 0.00
otbn_tl_intg_err 16.000s 111.922us 1 1 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 52.000s 336.521us 1 1 100.00
V2S prim_fsm_check otbn_sec_cm 15.000s 159.456us 0 1 0.00
V2S prim_count_check otbn_sec_cm 15.000s 159.456us 0 1 0.00
V2S sec_cm_mem_scramble otbn_smoke 9.000s 138.878us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 6.000s 118.632us 0 1 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 7.000s 18.193us 0 1 0.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 16.000s 111.922us 1 1 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 7.000s 65.008us 0 1 0.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 7.000s 18.193us 0 1 0.00
otbn_dmem_err 6.000s 118.632us 0 1 0.00
otbn_zero_state_err_urnd 7.000s 33.622us 0 1 0.00
otbn_illegal_mem_acc 5.000s 14.391us 1 1 100.00
otbn_sec_cm 15.000s 159.456us 0 1 0.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 15.000s 159.456us 0 1 0.00
V2S sec_cm_scramble_key_sideload otbn_single 5.000s 71.727us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 7.000s 18.193us 0 1 0.00
otbn_dmem_err 6.000s 118.632us 0 1 0.00
otbn_zero_state_err_urnd 7.000s 33.622us 0 1 0.00
otbn_illegal_mem_acc 5.000s 14.391us 1 1 100.00
otbn_sec_cm 15.000s 159.456us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 15.000s 159.456us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 7.000s 65.008us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 7.000s 18.193us 0 1 0.00
otbn_dmem_err 6.000s 118.632us 0 1 0.00
otbn_zero_state_err_urnd 7.000s 33.622us 0 1 0.00
otbn_illegal_mem_acc 5.000s 14.391us 1 1 100.00
otbn_sec_cm 15.000s 159.456us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 15.000s 159.456us 0 1 0.00
V2S sec_cm_data_reg_sw_sca otbn_single 5.000s 71.727us 0 1 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 5.000s 33.618us 0 1 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 5.000s 35.200us 1 1 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 22.000s 110.664us 0 1 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 22.000s 110.664us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 6.000s 32.351us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 15.000s 159.456us 0 1 0.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 15.000s 159.456us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 9.000s 218.362us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 15.000s 159.456us 0 1 0.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 15.000s 159.456us 0 1 0.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 5.000s 69.045us 0 1 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 5.000s 69.045us 0 1 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 4.000s 25.410us 1 1 100.00
V2S sec_cm_data_mem_sec_wipe otbn_single 5.000s 71.727us 0 1 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 5.000s 71.727us 0 1 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 5.000s 71.727us 0 1 0.00
V2S sec_cm_write_mem_integrity otbn_multi 32.000s 309.010us 0 1 0.00
V2S sec_cm_ctrl_flow_count otbn_single 5.000s 71.727us 0 1 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 5.000s 71.727us 0 1 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 8.000s 86.651us 0 1 0.00
V2S sec_cm_key_sideload otbn_single 5.000s 71.727us 0 1 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 15.000s 159.456us 0 1 0.00
V2S TOTAL 7 20 35.00
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 3.567m 1.238ms 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 18 41 43.90

Failure Buckets