ROM_CTRL/32KB Simulation Results

Wednesday October 08 2025 16:07:13 UTC

GitHub Revision: e4ce7cf

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	5.800s	184.893us	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	7.490s	624.661us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	3.510s	371.296us	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	5.020s	2.912ms	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	4.730s	534.517us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	4.040s	1.117ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	3.510s	371.296us	1	1	100.00
		rom_ctrl_csr_aliasing	4.730s	534.517us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	5.660s	125.557us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	3.990s	292.998us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	5.210s	735.428us	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	13.810s	6.880ms	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	8.420s	1.080ms	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	3.850s	124.250us	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	5.700s	167.875us	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	5.700s	167.875us	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	7.490s	624.661us	1	1	100.00
		rom_ctrl_csr_rw	3.510s	371.296us	1	1	100.00
		rom_ctrl_csr_aliasing	4.730s	534.517us	1	1	100.00
		rom_ctrl_same_csr_outstanding	5.010s	133.532us	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	7.490s	624.661us	1	1	100.00
		rom_ctrl_csr_rw	3.510s	371.296us	1	1	100.00
		rom_ctrl_csr_aliasing	4.730s	534.517us	1	1	100.00
		rom_ctrl_same_csr_outstanding	5.010s	133.532us	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	1.400m	12.868ms	1	1	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	21.740s	867.078us	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.756m	580.701us	0	1	0.00
		rom_ctrl_tl_intg_err	45.400s	891.971us	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.756m	580.701us	0	1	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	1.756m	580.701us	0	1	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.400m	12.868ms	1	1	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.400m	12.868ms	1	1	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.400m	12.868ms	1	1	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.400m	12.868ms	1	1	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.400m	12.868ms	1	1	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.756m	580.701us	0	1	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.756m	580.701us	0	1	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	5.800s	184.893us	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	5.800s	184.893us	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	5.800s	184.893us	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	45.400s	891.971us	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.400m	12.868ms	1	1	100.00
		rom_ctrl_kmac_err_chk	8.420s	1.080ms	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	1.400m	12.868ms	1	1	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.400m	12.868ms	1	1	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	1.400m	12.868ms	1	1	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	21.740s	867.078us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.756m	580.701us	0	1	0.00
V2S		TOTAL			3	4	75.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	56.710s	11.029ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' has 1 failures:
  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.31475439543245229489294301733796898532508733192565385056400545434489968238808
      Line 362, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 51419328ps failed at 51419328ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 51429745ps failed at 51429745ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'