ROM_CTRL/64KB Simulation Results

Wednesday October 08 2025 16:07:13 UTC

GitHub Revision: e4ce7cf

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	6.720s	768.853us	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	9.930s	4.998ms	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	5.620s	651.022us	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	7.060s	377.087us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	6.010s	214.516us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	7.850s	778.019us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	5.620s	651.022us	1	1	100.00
		rom_ctrl_csr_aliasing	6.010s	214.516us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	6.260s	698.460us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	6.860s	217.519us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	7.570s	2.020ms	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	19.500s	594.998us	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	14.530s	2.111ms	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	9.720s	4.164ms	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	9.110s	288.904us	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	9.110s	288.904us	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	9.930s	4.998ms	1	1	100.00
		rom_ctrl_csr_rw	5.620s	651.022us	1	1	100.00
		rom_ctrl_csr_aliasing	6.010s	214.516us	1	1	100.00
		rom_ctrl_same_csr_outstanding	8.990s	736.431us	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	9.930s	4.998ms	1	1	100.00
		rom_ctrl_csr_rw	5.620s	651.022us	1	1	100.00
		rom_ctrl_csr_aliasing	6.010s	214.516us	1	1	100.00
		rom_ctrl_same_csr_outstanding	8.990s	736.431us	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	2.982m	70.980ms	1	1	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	43.940s	1.624ms	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	8.287m	8.080ms	0	1	0.00
		rom_ctrl_tl_intg_err	54.560s	1.026ms	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	8.287m	8.080ms	0	1	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	8.287m	8.080ms	0	1	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.982m	70.980ms	1	1	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.982m	70.980ms	1	1	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.982m	70.980ms	1	1	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.982m	70.980ms	1	1	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.982m	70.980ms	1	1	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	8.287m	8.080ms	0	1	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	8.287m	8.080ms	0	1	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	6.720s	768.853us	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	6.720s	768.853us	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	6.720s	768.853us	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	54.560s	1.026ms	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.982m	70.980ms	1	1	100.00
		rom_ctrl_kmac_err_chk	14.530s	2.111ms	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	2.982m	70.980ms	1	1	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.982m	70.980ms	1	1	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	2.982m	70.980ms	1	1	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	43.940s	1.624ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	8.287m	8.080ms	0	1	0.00
V2S		TOTAL			3	4	75.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.065m	2.951ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:
  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.41836469523152745590084223035583251821886506414813624156473005224367077569985
      Line 172, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 173358973ps failed at 173358973ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 173358973ps failed at 173358973ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'