RV_TIMER Simulation Results

Wednesday October 08 2025 16:07:13 UTC

GitHub Revision: e4ce7cf

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.120s	149.093us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.640s	36.418us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.730s	13.119us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	1.910s	197.625us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.660s	63.473us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	0.760s	111.623us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.730s	13.119us	1	1	100.00
		rv_timer_csr_aliasing	0.660s	63.473us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	10.420s	98.623ms	0	1	0.00
V2	disabled	rv_timer_disabled	2.440s	2.733ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	4.425m	641.743ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	4.425m	641.743ms	1	1	100.00
V2	stress	rv_timer_stress_all	2.020s	599.984us	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.820s	39.573us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.650s	16.125us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.290s	86.543us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.290s	86.543us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.640s	36.418us	1	1	100.00
		rv_timer_csr_rw	0.730s	13.119us	1	1	100.00
		rv_timer_csr_aliasing	0.660s	63.473us	1	1	100.00
		rv_timer_same_csr_outstanding	0.690s	42.202us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.640s	36.418us	1	1	100.00
		rv_timer_csr_rw	0.730s	13.119us	1	1	100.00
		rv_timer_csr_aliasing	0.660s	63.473us	1	1	100.00
		rv_timer_same_csr_outstanding	0.690s	42.202us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	rv_timer_sec_cm	0.940s	134.915us	1	1	100.00
		rv_timer_tl_intg_err	1.610s	149.283us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.610s	149.283us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	0.830s	71.359us	0	1	0.00
V3	max_value	rv_timer_max	0.760s	91.134us	0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	18.750s	6.836ms	1	1	100.00
V3		TOTAL			1	3	33.33
		TOTAL			16	19	84.21

Failure Buckets

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:

  • Test rv_timer_min has 1 failures.

    • 0.rv_timer_min.8118203414480645351540468973687065372088644518730563851601303075036287177209
      Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log

        UVM_FATAL @  71358693 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x1b5e9504) == 0x1
        UVM_INFO @  71358693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.38912795120926688132927843491855987250754937761593565350534975683105596719107
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 98622681647 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x409dc704) == 0x1
        UVM_INFO @ 98622681647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.100656684486166706169738922307593320505083206985395751367220536355632677095210
      Line 74, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @  91133913 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @  91133913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---