SPI_DEVICE/1R1W Simulation Results

Wednesday October 08 2025 16:07:13 UTC

GitHub Revision: e4ce7cf

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	2.594m	104.981ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.160s	33.190us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.500s	299.980us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	25.480s	2.090ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	14.420s	308.072us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.190s	39.326us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.500s	299.980us	1	1	100.00
		spi_device_csr_aliasing	14.420s	308.072us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.950s	10.718us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.540s	60.725us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.970s	15.683us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.980s	26.103us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.970s	6.581us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.740s	158.103us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.740s	158.103us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	2.620s	548.485us	1	1	100.00
		spi_device_tpm_sts_read	1.020s	28.749us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	20.370s	5.186ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	8.670s	7.868ms	1	1	100.00
		spi_device_flash_all	35.710s	16.121ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	6.370s	359.567us	1	1	100.00
		spi_device_flash_all	35.710s	16.121ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	6.370s	359.567us	1	1	100.00
		spi_device_flash_all	35.710s	16.121ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	35.710s	16.121ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	6.550s	1.123ms	1	1	100.00
		spi_device_flash_all	35.710s	16.121ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	6.550s	1.123ms	1	1	100.00
		spi_device_flash_all	35.710s	16.121ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	6.550s	1.123ms	1	1	100.00
		spi_device_flash_all	35.710s	16.121ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	6.550s	1.123ms	1	1	100.00
		spi_device_flash_all	35.710s	16.121ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	6.550s	1.123ms	1	1	100.00
		spi_device_flash_all	35.710s	16.121ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	7.200s	4.790ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	5.090s	701.866us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	5.090s	701.866us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	5.090s	701.866us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	14.110s	1.584ms	1	1	100.00
		spi_device_read_buffer_direct	10.860s	7.124ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	5.090s	701.866us	1	1	100.00
		spi_device_flash_all	35.710s	16.121ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	35.710s	16.121ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	35.710s	16.121ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.490s	120.755us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.490s	120.755us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	2.594m	104.981ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	50.560s	13.568ms	1	1	100.00
V2	stress_all	spi_device_stress_all	2.887m	57.744ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.780s	15.600us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.970s	23.756us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.890s	1.138ms	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.890s	1.138ms	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.160s	33.190us	1	1	100.00
		spi_device_csr_rw	2.500s	299.980us	1	1	100.00
		spi_device_csr_aliasing	14.420s	308.072us	1	1	100.00
		spi_device_same_csr_outstanding	2.950s	214.853us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.160s	33.190us	1	1	100.00
		spi_device_csr_rw	2.500s	299.980us	1	1	100.00
		spi_device_csr_aliasing	14.420s	308.072us	1	1	100.00
		spi_device_same_csr_outstanding	2.950s	214.853us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.080s	173.869us	1	1	100.00
		spi_device_tl_intg_err	9.930s	385.835us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	9.930s	385.835us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	24.760s	5.903ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.6437464634046862540204805317885162649174844483309977360861705311105395720622
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @  19302877 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[22])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @  19302877 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @  19302877 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[918])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.66929398804375735052294671329222590722133929143024719392103271976527034975714
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   3998271 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf043f1 [111100000100001111110001] vs 0x0 [0])
        UVM_ERROR @   4019271 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd1a97a [110100011010100101111010] vs 0x0 [0])
        UVM_ERROR @   4035271 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x33755b [1100110111010101011011] vs 0x0 [0])
        UVM_ERROR @   4126271 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa68e2c [101001101000111000101100] vs 0x0 [0])
        UVM_ERROR @   4219271 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xcd2a1a [110011010010101000011010] vs 0x0 [0])