SPI_HOST Simulation Results

Wednesday October 08 2025 16:07:13 UTC

GitHub Revision: e4ce7cf

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	36.000s	10.190ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	45.062us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	49.817us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	3.000s	106.111us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	1.000s	229.867us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	1.000s	33.123us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	49.817us	1	1	100.00
		spi_host_csr_aliasing	1.000s	229.867us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	1.000s	15.988us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	1.000s	27.844us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	2.000s	23.285us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.000s	85.554us	1	1	100.00
		spi_host_error_cmd	1.000s	61.771us	1	1	100.00
		spi_host_event	13.000s	6.530ms	1	1	100.00
V2	clock_rate	spi_host_speed	7.000s	366.471us	1	1	100.00
V2	speed	spi_host_speed	7.000s	366.471us	1	1	100.00
V2	chip_select_timing	spi_host_speed	7.000s	366.471us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	18.000s	1.014ms	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	1.000s	27.694us	1	1	100.00
V2	cpol_cpha	spi_host_speed	7.000s	366.471us	1	1	100.00
V2	full_cycle	spi_host_speed	7.000s	366.471us	1	1	100.00
V2	duplex	spi_host_smoke	36.000s	10.190ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	36.000s	10.190ms	1	1	100.00
V2	stress_all	spi_host_stress_all	2.000s	94.454us	1	1	100.00
V2	spien	spi_host_spien	3.000s	1.027ms	1	1	100.00
V2	stall	spi_host_status_stall	23.000s	2.409ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	17.000s	9.216ms	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	3.000s	85.554us	1	1	100.00
V2	alert_test	spi_host_alert_test	2.000s	41.571us	1	1	100.00
V2	intr_test	spi_host_intr_test	1.000s	36.104us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	2.000s	50.892us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	2.000s	50.892us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	45.062us	1	1	100.00
		spi_host_csr_rw	2.000s	49.817us	1	1	100.00
		spi_host_csr_aliasing	1.000s	229.867us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	19.908us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	45.062us	1	1	100.00
		spi_host_csr_rw	2.000s	49.817us	1	1	100.00
		spi_host_csr_aliasing	1.000s	229.867us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	19.908us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	2.000s	330.818us	1	1	100.00
		spi_host_sec_cm	2.000s	106.545us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	2.000s	330.818us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	3.950m	200.000ms	0	1	0.00
		TOTAL			25	26	96.15

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 0.spi_host_upper_range_clkdiv.23952377568204757975855245412239364949048446357746863116907937308308808949965
      Line 134, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---