SRAM_CTRL/MAIN Simulation Results

Wednesday October 08 2025 16:07:13 UTC

GitHub Revision: e4ce7cf

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	13.970s	1.954ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.900s	58.843us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.920s	32.147us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.350s	48.223us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.790s	61.973us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.990s	654.126us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.920s	32.147us	1	1	100.00
		sram_ctrl_csr_aliasing	0.790s	61.973us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.652m	16.455ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.784m	4.865ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	6.529m	32.144ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	5.562m	24.553ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	21.567m	24.472ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	10.191m	62.584ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	43.350s	37.501ms	1	1	100.00
V2	executable	sram_ctrl_executable	7.204m	8.426ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	44.080s	1.284ms	1	1	100.00
		sram_ctrl_partial_access_b2b	5.800m	19.804ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	16.090s	11.770ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	16.280s	2.002ms	1	1	100.00
		sram_ctrl_throughput_w_readback	24.040s	4.034ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	13.607m	14.120ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.480s	353.267us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	12.408m	226.991ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.950s	40.790us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.340s	116.889us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.340s	116.889us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.900s	58.843us	1	1	100.00
		sram_ctrl_csr_rw	0.920s	32.147us	1	1	100.00
		sram_ctrl_csr_aliasing	0.790s	61.973us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.790s	24.046us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.900s	58.843us	1	1	100.00
		sram_ctrl_csr_rw	0.920s	32.147us	1	1	100.00
		sram_ctrl_csr_aliasing	0.790s	61.973us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.790s	24.046us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	19.850s	15.436ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.930s	6.973us	0	1	0.00
		sram_ctrl_tl_intg_err	1.940s	209.599us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.930s	6.973us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.940s	209.599us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	13.607m	14.120ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	13.607m	14.120ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.920s	32.147us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	7.204m	8.426ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	7.204m	8.426ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	7.204m	8.426ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	43.350s	37.501ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.310s	1.332ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	19.850s	15.436ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	3.350s	672.048us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	13.970s	1.954ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	13.970s	1.954ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	7.204m	8.426ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.930s	6.973us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	43.350s	37.501ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.930s	6.973us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.930s	6.973us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	13.970s	1.954ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.930s	6.973us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	23.100s	2.348ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.37479587013918168405508105797188391522310380610437425725588603892788730800002
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 672047517 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x33) != exp (0x3d)
        UVM_INFO @ 672047517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.41849928186094865257478214199924981555821881699858489196963185820295746897996
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   6972966 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   6972966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---