UART Simulation Results

Wednesday October 08 2025 16:07:13 UTC

GitHub Revision: e4ce7cf

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.400s	449.401us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.290s	1.038ms	1	1	100.00
V1	csr_rw	uart_csr_rw	0.630s	15.617us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.190s	395.493us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.770s	66.851us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.840s	72.717us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.630s	15.617us	1	1	100.00
		uart_csr_aliasing	0.770s	66.851us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	10.750s	7.626ms	1	1	100.00
V2	parity	uart_smoke	1.400s	449.401us	1	1	100.00
		uart_tx_rx	10.750s	7.626ms	1	1	100.00
V2	parity_error	uart_intr	11.820s	32.805ms	1	1	100.00
		uart_rx_parity_err	10.180s	49.656ms	1	1	100.00
V2	watermark	uart_tx_rx	10.750s	7.626ms	1	1	100.00
		uart_intr	11.820s	32.805ms	1	1	100.00
V2	fifo_full	uart_fifo_full	1.519m	85.068ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	27.530s	179.425ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	41.630s	132.793ms	1	1	100.00
V2	rx_frame_err	uart_intr	11.820s	32.805ms	1	1	100.00
V2	rx_break_err	uart_intr	11.820s	32.805ms	1	1	100.00
V2	rx_timeout	uart_intr	11.820s	32.805ms	1	1	100.00
V2	perf	uart_perf	1.108m	10.965ms	1	1	100.00
V2	sys_loopback	uart_loopback	14.890s	10.018ms	1	1	100.00
V2	line_loopback	uart_loopback	14.890s	10.018ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	1.130s	451.417us	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	29.030s	27.783ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.720s	801.808us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	2.880s	2.558ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	8.175m	154.610ms	1	1	100.00
V2	stress_all	uart_stress_all	9.283m	315.094ms	1	1	100.00
V2	alert_test	uart_alert_test	0.730s	38.795us	1	1	100.00
V2	intr_test	uart_intr_test	0.690s	11.350us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.500s	195.099us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.500s	195.099us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.290s	1.038ms	1	1	100.00
		uart_csr_rw	0.630s	15.617us	1	1	100.00
		uart_csr_aliasing	0.770s	66.851us	1	1	100.00
		uart_same_csr_outstanding	0.830s	56.625us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.290s	1.038ms	1	1	100.00
		uart_csr_rw	0.630s	15.617us	1	1	100.00
		uart_csr_aliasing	0.770s	66.851us	1	1	100.00
		uart_same_csr_outstanding	0.830s	56.625us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	0.960s	42.556us	1	1	100.00
		uart_tl_intg_err	1.220s	47.665us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.220s	47.665us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	24.950s	14.198ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxFrameErr has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.22660223533636457910797189899241159182180259921975822104566336877024404876884
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 135971491 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
        UVM_ERROR @ 135971491 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxFrameErr
        UVM_ERROR @ 135971491 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
        UVM_ERROR @ 136858065 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
        UVM_ERROR @ 136858065 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxFrameErr