CHIP Simulation Results

Wednesday October 08 2025 16:07:13 UTC

GitHub Revision: `e4ce7cf`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.980m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.980m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	30.960s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	17.724s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	15.963s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	9.032m	6.569ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	9.032m	6.569ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	9.032m	6.569ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	31.660s	10.240us	0	1	0.00
		chip_sw_example_manufacturer	14.050s		0	1	0.00
		chip_sw_example_concurrency	5.122m	4.937ms	1	1	100.00
		chip_sw_uart_smoketest_signed	12.255s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	10.540s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	10.110s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	10.110s		0	1	0.00
V1	xbar_smoke	xbar_smoke	19.220s	57.056us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.837m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	9.264m	7.315ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.466m	3.494ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	17.285s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	26.022s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	12.595s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	18.139s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	2.940s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.940s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.096m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.021m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.385m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.385m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.899m	4.733ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.616m	4.021ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.789m	13.289ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.284s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	11.893s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	5.213m	6.328ms	0	1	0.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	6.989m	5.679ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	22.993m	18.018ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	22.993m	18.018ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	12.178s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.259m	5.246ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.259m	5.246ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	7.865m	18.019ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.884m	5.227ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	7.013m	4.640ms	1	1	100.00
		chip_sw_aes_idle	4.163m	5.322ms	1	1	100.00
		chip_sw_hmac_enc_idle	5.343m	5.986ms	1	1	100.00
		chip_sw_kmac_idle	3.747m	4.538ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	12.876m	12.027ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	14.743m	12.019ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	12.026m	12.027ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	14.513m	12.019ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	11.991s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.475s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.138s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.830s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.279s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.021s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.688s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	11.991s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.475s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.138s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.830s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.279s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.021s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.688s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	12.318s		0	1	0.00
		chip_sw_aes_enc_jitter_en	38.880s	10.260us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	41.700s	10.220us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	36.560s	10.160us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	37.040s	10.280us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.508s		0	1	0.00
		chip_sw_clkmgr_jitter	4.139m	4.345ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.323m	3.710ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	15.911s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	37.040s	10.300us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	54.150s	10.240us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	37.440s	10.360us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	36.710s	10.180us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	37.150s	10.260us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	17.201s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	13.664s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	13.085s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	11.712s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	21.837m	13.639ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	8.640m	12.098ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	5.259m	5.246ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	13.235s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	8.640m	12.098ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	16.694s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	12.431s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	13.353s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	13.623s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	14.439s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	21.837m	13.639ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.789m	13.289ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	24.061m	20.027ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	6.896m	7.074ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	11.857m	10.465ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.750m	5.132ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	21.837m	13.639ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	18.643s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	12.043s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	21.837m	13.639ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	11.741s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	11.857m	10.465ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	12.346s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	13.181s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	13.510s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	14.389s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	11.843s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	12.138s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	12.043s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	12.312s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	13.091s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	12.312s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	12.312s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	12.312s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	8.995m	8.769ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	25.612s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	19.302s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	16.988s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	14.361s		0	1	0.00
		chip_sw_lc_ctrl_transition	12.312s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	5.993m	5.908ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	11.514m	15.369ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	13.668s		0	1	0.00
		chip_prim_tl_access	17.008m	24.814ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	11.991s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.475s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.138s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.830s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.279s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.021s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.688s		0	1	0.00
		chip_rv_dm_lc_disabled	5.213m	6.328ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.406m	5.658ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	38.880s	10.260us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.250m	3.587ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.163m	5.322ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.067m	4.497ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	41.700s	10.220us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.343m	5.986ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.778m	4.307ms	1	1	100.00
		chip_sw_kmac_mode_kmac	5.743m	4.513ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	37.040s	10.280us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	5.993m	5.908ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	12.312s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	33.330s	10.360us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	8.216m	5.934ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.747m	4.538ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.863s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.863s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	15.946s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.097m	3.493ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	12.693s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	5.993m	5.908ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	36.560s	10.160us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	12.189s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	12.318s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	7.013m	4.640ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	7.013m	4.640ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	7.013m	4.640ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	9.431m	5.881ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	11.514m	15.369ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	11.514m	15.369ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	8.415m	5.871ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.508s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	13.668s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	21.837m	13.639ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.385m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	12.312s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	9.431m	5.881ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	5.993m	5.908ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.415m	5.871ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.639m	4.586ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	9.431m	5.881ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	5.993m	5.908ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.415m	5.871ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.639m	4.586ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	12.312s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	13.455s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	13.091s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	25.612s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	19.302s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	16.988s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	14.361s		0	1	0.00
		chip_sw_lc_ctrl_transition	12.312s		0	1	0.00
		chip_prim_tl_access	17.008m	24.814ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	17.008m	24.814ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	13.045s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	12.155s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	13.664s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	12.318s		0	1	0.00
		chip_sw_aes_enc_jitter_en	38.880s	10.260us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	41.700s	10.220us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	36.560s	10.160us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	37.040s	10.280us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.508s		0	1	0.00
		chip_sw_clkmgr_jitter	4.139m	4.345ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	6.649m	5.881ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	6.649m	5.881ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	4.465m	4.150ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.497m	4.873ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	4.242m	3.892ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.673m	5.569ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	5.100m	5.552ms	0	1	0.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	5.903m	5.803ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.639m	4.586ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	24.061m	20.027ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	24.061m	20.027ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.551m	4.122ms	1	1	100.00
		chip_sw_aon_timer_smoketest	5.020m	4.913ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.665m	5.274ms	1	1	100.00
		chip_sw_csrng_smoketest	4.205m	4.665ms	1	1	100.00
		chip_sw_gpio_smoketest	3.434m	4.700ms	1	1	100.00
		chip_sw_hmac_smoketest	4.604m	5.032ms	1	1	100.00
		chip_sw_kmac_smoketest	4.968m	4.860ms	1	1	100.00
		chip_sw_otbn_smoketest	5.835m	5.642ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	4.386m	4.568ms	1	1	100.00
		chip_sw_rv_plic_smoketest	4.548m	5.506ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.724m	5.269ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.904m	5.369ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	4.000m	5.523ms	1	1	100.00
		chip_sw_uart_smoketest	4.243m	4.999ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	12.203s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	12.255s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.837m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	13.551s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.241m	3.832ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.796m	4.889ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	4.149m	5.103ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.845m	6.205ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	11.460s		0	1	0.00
		chip_rv_dm_lc_disabled	5.213m	6.328ms	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	14.866s		0	1	0.00
		chip_sw_lc_walkthrough_prod	13.063s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	15.986s		0	1	0.00
		chip_sw_lc_walkthrough_rma	11.581s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	11.460s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	12.689s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	13.275s		0	1	0.00
		rom_volatile_raw_unlock	12.465s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	11.917s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	55.086s		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.681m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	3.891m	4.647ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	3.891m	4.647ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	10.110s		0	1	0.00
		chip_same_csr_outstanding	8.510s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	10.110s		0	1	0.00
		chip_same_csr_outstanding	8.510s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	3.072m	482.689us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	9.060s	12.324us	1	1	100.00
		xbar_smoke_large_delays	4.174m	2.169ms	1	1	100.00
		xbar_smoke_slow_rsp	5.657m	2.037ms	1	1	100.00
		xbar_random_zero_delays	35.630s	35.016us	1	1	100.00
		xbar_random_large_delays	19.966m	10.150ms	1	1	100.00
		xbar_random_slow_rsp	3.808m	1.418ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	48.600s	33.165us	1	1	100.00
		xbar_error_and_unmapped_addr	20.210s	13.141us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	41.470s	98.991us	1	1	100.00
		xbar_error_and_unmapped_addr	20.210s	13.141us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.433m	79.278us	1	1	100.00
		xbar_access_same_device_slow_rsp	18.477m	6.416ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	42.180s	35.379us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	3.771m	176.269us	1	1	100.00
		xbar_stress_all_with_error	2.241m	109.622us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	12.371m	585.401us	1	1	100.00
		xbar_stress_all_with_reset_error	26.841m	1.258ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	11.923s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	11.598s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	13.167s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	13.316s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	13.649s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	11.365s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.898s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	11.564s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	14.900s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	13.594s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	11.964s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	11.684s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	12.710s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	39.935s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	42.671s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	45.464s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	38.289s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	36.494s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	38.512s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	37.946s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	28.699s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	28.443s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	35.463s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	35.567s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	35.729s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	34.239s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	28.073s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	29.832s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	19.313s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	14.691s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	14.358s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	12.920s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	13.531s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	12.614s		0	1	0.00
		rom_e2e_asm_init_dev	12.286s		0	1	0.00
		rom_e2e_asm_init_prod	11.853s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.806s		0	1	0.00
		rom_e2e_asm_init_rma	12.212s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	12.176s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	11.779s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	14.065s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	13.108s		0	1	0.00
V2		TOTAL			63	205	30.73
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.269m	5.558ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.456m	3.215ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.981s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.515s		0	1	0.00
		rom_e2e_jtag_debug_rma	14.392s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	12.090s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	21.837m	13.639ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	18.252s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	18.393m	15.777ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	12.792s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	12.652s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.981s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.515s		0	1	0.00
		rom_e2e_jtag_debug_rma	14.392s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.819s		0	1	0.00
		rom_e2e_jtag_inject_dev	12.004s		0	1	0.00
		rom_e2e_jtag_inject_rma	13.503s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	11.797s		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	22.309m	15.518ms	1	1	100.00
		chip_sw_entropy_src_kat_test	3.897m	4.866ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	4.979m	4.946ms	1	1	100.00
		chip_plic_all_irqs_0	9.457m	6.088ms	1	1	100.00
		chip_plic_all_irqs_10	10.966m	7.137ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.628m	3.854ms	1	1	100.00
		chip_sw_dma_abort	4.871m	5.409ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	11.367s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	11.443s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	12.291s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	11.359s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	11.765s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.943s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	12.223s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	12.456s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	12.253s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	12.125s		0	1	0.00
		chip_sw_entropy_src_smoketest	4.565m	5.778ms	1	1	100.00
		chip_sw_mbx_smoketest	5.106m	5.880ms	1	1	100.00
		TOTAL			77	250	30.80

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.108434653341870439679975993499676094952091383599968267034014928802559270348009
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (9 packages loaded, 15 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 3.132s, Critical Path: 0.07s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.107899693840787958713127363584335614826719066180895561046599693633313889815125
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 131.152s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.21100380326678937741208463849144956847026406683301379856444549610618039480690
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 113.953s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.25703890167004042469396539422485127076389711179660471087594928052729463086912
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 110.273s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.82519722882982400436652360660047558465845889238283106400722394703454118546623
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 108.211s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.65464366277159016184879740365018276898408055109210883824514235230614303437745
    Line 380, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.46631519736385818354910981310978062900502595573987269439409306893920774746571
    Line 385, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.114499456069059090808613135610212016866409769644705787603013904160631184607155
    Line 378, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.160001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.34077405904402614592407052748213772928761342150521922901657273758013726178068
    Line 380, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.98379146658910860460137551037161173107999081549193235203960516233787577175157
    Line 385, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.300001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.70001748465080268999562096723779179218608715549171330801944221323709191333442
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.32792157076346256446674925228992592937301358936651855579127994916444775409250
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.28793080793795967780325833612218363650038613898712883321127570032079453621463
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.26712789946027123836651708570788294781647328289735907750042126928055964513298
Line 427, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20026.707559 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20026.707559 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.17786438487593754318093664499593816782906273311291613891370667739270299194216
Line 387, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18018.440465 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.440465 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.43720013976211816488895322507678433203068118551758589522758726423284612332888
Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18018.610201 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.610201 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.32792266263706681111443794221951851857863119522165983616991256905433017709610
Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12026.857050 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.857050 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

0.chip_sw_clkmgr_off_kmac_trans.65603207645451567493451482072416120789744093178308030965088684971496359773186
Line 397, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12026.968881 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.968881 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.52707250487194548287101211400600520675275391167193056457198424002573102672669
Line 395, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12018.547762 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.547762 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.60184819102680593140886318098170716779248597474093643905465918007853811668329
Line 410, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 5907.839450 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (1025210146926905962932494888643744708360717679589716192750968626577288104321311494610999129058489988455163234960520339139163079448672071961939339314027612 [0x13931f70aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd395c5af817f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 5907.839450 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.108033765389240002237448724533933237398692517299810205556545802717583354084214
Line 401, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 8769.338765 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (458316821429743564661254396347720023149398009351912290950132134311411931107078499509952888170949122194250509085103389739261065827975601757167014381968476 [0x8c034b9aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd38e9684487f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 8769.338765 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47283) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.91943767208913438328152507606679949481942555092416871895194623912159210810354
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4733.351025 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47283) { a_addr: 'h30480000  a_data: 'h9dacb716  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h10  a_opcode: 'h1  a_user: 'h2489c  d_param: 'h0  d_source: 'h10  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4733.351025 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.2911430023071045437862747689719182775915587269535668674218770132399225676725
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 4021.188963 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47283) { a_addr: 'h30480000  a_data: 'h848409a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h16  a_opcode: 'h1  a_user: 'h248c0  d_param: 'h0  d_source: 'h16  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4021.188963 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.115481925969457312803732450803109561778429295163969856639645416216243199460157
    Line 1357, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.9742520799617897434163725877705459210224528450916152899048778801594225729100
    Line 425, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3494.410962 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3494.410962 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.5688570653954261307545088138224424546046072463606700625939632472569638531351
    Line 623, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 10464.804980 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 10464.804980 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.20246058871976269725463418091834455192824239199780875338596810663608230691708
    Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 4150.466815 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 4150.466815 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.20919055798512481964115370634729445981436384603277378219803673122340135573010
    Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4873.080580 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4873.080580 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.65574754768810983774039556567846540599564176884959928442261995220284537162781
    Line 388, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 5245.699720 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 5245.699720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == * has 1 failures:
- Test chip_sw_rv_core_ibex_rnd has 1 failures.
  - 0.chip_sw_rv_core_ibex_rnd.31848831368276234559743498461619049574278591039871649755974309208310591897898
    Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_rnd/latest/run.log
```
  UVM_ERROR @ 5551.742854 us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == 0
  UVM_INFO @ 5551.742854 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.27350814680072183356245544591674402522998038857276475533507584617552437833775
    Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5569.166141 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5569.166141 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.10254759210520415105670051451100806687379682030346379874094807765746144524990
    Line 404, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.33098664650914173023502354918993542450984420284680496828098375630157677002103
    Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 4647.309504 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 4647.309504 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 1 failures:
- Test chip_sw_clkmgr_off_hmac_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_hmac_trans.72785736544229897732010011974712644541948098550100186629650479360133651369607
    Line 413, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log
```
  UVM_ERROR @ 12018.553080 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.553080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.58280066134890129724591009997141780214619070028360785037355550816367621322759
    Line 377, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 13288.942300 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 13288.942300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.53151438522341364010045116275742461337413892247361431080111265267725125261899
    Line 227, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 6327.729711 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x40780 read out mismatch
  UVM_INFO @ 6327.729711 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.45558767076475739720629128664792855207428528866580854369992070269875826652607
    Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.99032465961172195296745371579263774564883126901137516814430627035725705588566
    Line 397, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 5409.230560 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 5409.230560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```