DMA Simulation Results

Thursday October 09 2025 16:09:14 UTC

GitHub Revision: 677ee3d

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	5.000s	319.370us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	4.000s	258.776us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	6.000s	1.927ms	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	2.000s	22.570us	1	1	100.00
V1	csr_rw	dma_csr_rw	2.000s	110.645us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	7.000s	777.394us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	4.000s	267.075us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	2.000s	84.224us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	2.000s	110.645us	1	1	100.00
		dma_csr_aliasing	4.000s	267.075us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	46.000s	11.793ms	1	1	100.00
V2	dma_memory_tl_error	dma_memory_stress	2.967m	77.276ms	1	1	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	5.467m	134.239ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	5.467m	134.239ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	2.967m	77.276ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	3.700m	17.830ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	5.467m	134.239ms	1	1	100.00
V2	dma_abort	dma_abort	8.000s	743.077us	1	1	100.00
V2	dma_stress_all	dma_stress_all	2.183m	9.649ms	1	1	100.00
V2	alert_test	dma_alert_test	2.000s	15.381us	1	1	100.00
V2	intr_test	dma_intr_test	2.000s	13.459us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	2.000s	283.703us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	2.000s	283.703us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	2.000s	22.570us	1	1	100.00
		dma_csr_rw	2.000s	110.645us	1	1	100.00
		dma_csr_aliasing	4.000s	267.075us	1	1	100.00
		dma_same_csr_outstanding	2.000s	23.108us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	2.000s	22.570us	1	1	100.00
		dma_csr_rw	2.000s	110.645us	1	1	100.00
		dma_csr_aliasing	4.000s	267.075us	1	1	100.00
		dma_same_csr_outstanding	2.000s	23.108us	1	1	100.00
V2		TOTAL			10	10	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	14.000s	182.131us	1	1	100.00
		dma_generic_stress	3.700m	17.830ms	1	1	100.00
		dma_handshake_stress	5.467m	134.239ms	1	1	100.00
V2S	dma_config_lock	dma_config_lock	8.000s	660.576us	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	3.000s	462.889us	1	1	100.00
		dma_sec_cm	2.000s	27.437us	1	1	100.00
V2S		TOTAL			4	4	100.00
	Unmapped tests	dma_short_transfer	1.133m	3.933ms	1	1	100.00
		dma_longer_transfer	2.000s	369.102us	1	1	100.00
		dma_stress_all_with_rand_reset	7.000s	450.590us	0	1	0.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.112142256164526794116567985994242045499922217125363633028363100876377880355089
      Line 107, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  450590364ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @  450590364ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---