EDN Simulation Results

Thursday October 09 2025 16:09:14 UTC

GitHub Revision: 677ee3d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 0.900s 19.355us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.910s 25.238us 1 1 100.00
V1 csr_rw edn_csr_rw 0.960s 20.021us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 2.340s 121.263us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.050s 42.789us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 0.950s 82.909us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.960s 20.021us 1 1 100.00
edn_csr_aliasing 1.050s 42.789us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 1.410s 52.876us 1 1 100.00
V2 csrng_commands edn_genbits 1.410s 52.876us 1 1 100.00
V2 genbits edn_genbits 1.410s 52.876us 1 1 100.00
V2 interrupts edn_intr 0.850s 38.136us 1 1 100.00
V2 alerts edn_alert 1.060s 99.511us 1 1 100.00
V2 errs edn_err 0.820s 25.928us 1 1 100.00
V2 disable edn_disable 0.770s 32.911us 1 1 100.00
edn_disable_auto_req_mode 0.990s 91.595us 1 1 100.00
V2 stress_all edn_stress_all 2.320s 117.323us 1 1 100.00
V2 intr_test edn_intr_test 0.990s 13.793us 1 1 100.00
V2 alert_test edn_alert_test 0.900s 38.303us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 2.810s 113.479us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 2.810s 113.479us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.910s 25.238us 1 1 100.00
edn_csr_rw 0.960s 20.021us 1 1 100.00
edn_csr_aliasing 1.050s 42.789us 1 1 100.00
edn_same_csr_outstanding 1.160s 125.841us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.910s 25.238us 1 1 100.00
edn_csr_rw 0.960s 20.021us 1 1 100.00
edn_csr_aliasing 1.050s 42.789us 1 1 100.00
edn_same_csr_outstanding 1.160s 125.841us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 6.120s 2.889ms 1 1 100.00
edn_tl_intg_err 1.550s 145.893us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 0.780s 48.472us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 1.060s 99.511us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 6.120s 2.889ms 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 6.120s 2.889ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 6.120s 2.889ms 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 6.120s 2.889ms 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.060s 99.511us 1 1 100.00
edn_sec_cm 6.120s 2.889ms 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.060s 99.511us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 1.550s 145.893us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets