HMAC Simulation Results

Thursday October 09 2025 16:09:14 UTC

GitHub Revision: 677ee3d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 2.280s 212.003us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.840s 64.225us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.810s 30.463us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 4.040s 1.479ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 2.460s 249.196us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.070s 50.143us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.810s 30.463us 1 1 100.00
hmac_csr_aliasing 2.460s 249.196us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 39.240s 4.261ms 1 1 100.00
V2 back_pressure hmac_back_pressure 1.067m 2.502ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.567m 7.050ms 1 1 100.00
hmac_test_sha384_vectors 18.300s 499.651us 1 1 100.00
hmac_test_sha512_vectors 6.445m 68.275ms 1 1 100.00
hmac_test_hmac256_vectors 6.420s 899.231us 1 1 100.00
hmac_test_hmac384_vectors 9.150s 891.244us 1 1 100.00
hmac_test_hmac512_vectors 6.380s 1.262ms 1 1 100.00
V2 burst_wr hmac_burst_wr 15.890s 3.484ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 4.052m 2.117ms 1 1 100.00
V2 error hmac_error 29.760s 3.347ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 31.360s 862.462us 1 1 100.00
V2 save_and_restore hmac_smoke 2.280s 212.003us 1 1 100.00
hmac_long_msg 39.240s 4.261ms 1 1 100.00
hmac_back_pressure 1.067m 2.502ms 1 1 100.00
hmac_datapath_stress 4.052m 2.117ms 1 1 100.00
hmac_burst_wr 15.890s 3.484ms 1 1 100.00
hmac_stress_all 2.389m 4.324ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 2.280s 212.003us 1 1 100.00
hmac_long_msg 39.240s 4.261ms 1 1 100.00
hmac_back_pressure 1.067m 2.502ms 1 1 100.00
hmac_datapath_stress 4.052m 2.117ms 1 1 100.00
hmac_wipe_secret 31.360s 862.462us 1 1 100.00
hmac_test_sha256_vectors 3.567m 7.050ms 1 1 100.00
hmac_test_sha384_vectors 18.300s 499.651us 1 1 100.00
hmac_test_sha512_vectors 6.445m 68.275ms 1 1 100.00
hmac_test_hmac256_vectors 6.420s 899.231us 1 1 100.00
hmac_test_hmac384_vectors 9.150s 891.244us 1 1 100.00
hmac_test_hmac512_vectors 6.380s 1.262ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 2.280s 212.003us 1 1 100.00
hmac_long_msg 39.240s 4.261ms 1 1 100.00
hmac_back_pressure 1.067m 2.502ms 1 1 100.00
hmac_datapath_stress 4.052m 2.117ms 1 1 100.00
hmac_burst_wr 15.890s 3.484ms 1 1 100.00
hmac_error 29.760s 3.347ms 1 1 100.00
hmac_wipe_secret 31.360s 862.462us 1 1 100.00
hmac_test_sha256_vectors 3.567m 7.050ms 1 1 100.00
hmac_test_sha384_vectors 18.300s 499.651us 1 1 100.00
hmac_test_sha512_vectors 6.445m 68.275ms 1 1 100.00
hmac_test_hmac256_vectors 6.420s 899.231us 1 1 100.00
hmac_test_hmac384_vectors 9.150s 891.244us 1 1 100.00
hmac_test_hmac512_vectors 6.380s 1.262ms 1 1 100.00
hmac_stress_all 2.389m 4.324ms 1 1 100.00
V2 stress_all hmac_stress_all 2.389m 4.324ms 1 1 100.00
V2 alert_test hmac_alert_test 0.600s 14.178us 1 1 100.00
V2 intr_test hmac_intr_test 0.610s 18.155us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.510s 449.193us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.510s 449.193us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.840s 64.225us 1 1 100.00
hmac_csr_rw 0.810s 30.463us 1 1 100.00
hmac_csr_aliasing 2.460s 249.196us 1 1 100.00
hmac_same_csr_outstanding 2.140s 119.732us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.840s 64.225us 1 1 100.00
hmac_csr_rw 0.810s 30.463us 1 1 100.00
hmac_csr_aliasing 2.460s 249.196us 1 1 100.00
hmac_same_csr_outstanding 2.140s 119.732us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.800s 90.525us 1 1 100.00
hmac_tl_intg_err 2.110s 456.044us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.110s 456.044us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 2.280s 212.003us 1 1 100.00
V3 stress_reset hmac_stress_reset 0.910s 38.591us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 5.420m 4.812ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 3.090s 778.014us 1 1 100.00
TOTAL 28 28 100.00