I2C Simulation Results

Thursday October 09 2025 16:09:14 UTC

GitHub Revision: 677ee3d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	56.640s	3.219ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	8.980s	7.112ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.690s	22.788us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.660s	33.376us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.150s	312.796us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.500s	206.286us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.060s	33.933us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.660s	33.376us	1	1	100.00
		i2c_csr_aliasing	1.500s	206.286us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.070s	92.017us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	13.031m	33.511ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	1.850s	304.398us	1	1	100.00
V2	host_override	i2c_host_override	0.980s	14.968us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.885m	11.515ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.013m	2.843ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	0.940s	153.470us	1	1	100.00
		i2c_host_fifo_fmt_empty	5.070s	4.834ms	1	1	100.00
		i2c_host_fifo_reset_rx	2.470s	595.442us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	39.310s	8.524ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	9.800s	1.510ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	5.240s	174.444us	1	1	100.00
V2	target_glitch	i2c_target_glitch	2.280s	539.966us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	1.843m	18.226ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.570s	2.510ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	34.140s	4.395ms	1	1	100.00
		i2c_target_intr_smoke	3.960s	1.657ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	0.960s	738.003us	1	1	100.00
		i2c_target_fifo_reset_tx	0.810s	113.215us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	3.157m	53.537ms	1	1	100.00
		i2c_target_stress_rd	34.140s	4.395ms	1	1	100.00
		i2c_target_intr_stress_wr	5.520s	7.426ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.520s	1.513ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	1.207m	2.417ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	2.440s	650.523us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	1.850s	502.671us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.570s	737.767us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.350s	491.465us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	1.850s	304.398us	1	1	100.00
		i2c_host_perf_precise	3.380s	832.471us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	9.800s	1.510ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	1.220s	77.902us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.000s	2.369ms	1	1	100.00
		i2c_target_nack_acqfull_addr	1.840s	537.076us	1	1	100.00
		i2c_target_nack_txstretch	1.070s	658.575us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	13.770s	2.026ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.970s	412.443us	1	1	100.00
V2	alert_test	i2c_alert_test	0.830s	18.068us	1	1	100.00
V2	intr_test	i2c_intr_test	0.890s	136.299us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.920s	119.872us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.920s	119.872us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.690s	22.788us	1	1	100.00
		i2c_csr_rw	0.660s	33.376us	1	1	100.00
		i2c_csr_aliasing	1.500s	206.286us	1	1	100.00
		i2c_same_csr_outstanding	0.770s	194.382us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.690s	22.788us	1	1	100.00
		i2c_csr_rw	0.660s	33.376us	1	1	100.00
		i2c_csr_aliasing	1.500s	206.286us	1	1	100.00
		i2c_same_csr_outstanding	0.770s	194.382us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	1.140s	184.753us	1	1	100.00
		i2c_sec_cm	0.930s	163.342us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.140s	184.753us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	46.040s	1.146ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.020s	330.077us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	7.260s	4.010ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.59274999246846857390624738694423024640966104403671598777422507855620520795645
      Line 94, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1145608024 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1145608024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.108531917771486107924028460163054349641181481329869536865808968488497044521938
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4009660617 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4009660617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.40961606716872042506349022988195519590018814175649443671788979667268228187496
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  92016723 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  92016723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.9533703618052410295300219238619253394370137231169590248764355130793261005933
      Line 118, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 33511384307 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @5238147
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.95492223098624468129399969606465751535199495899152014809241124517106848732218
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 539966149 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 539966149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.32819249848015391539092481272508313014741576146282455773554396088472811866410
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 330077083 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 68 [0x44])
        UVM_INFO @ 330077083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---