| V1 |
smoke |
keymgr_dpe_smoke |
16.370s |
3.814ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
keymgr_dpe_csr_hw_reset |
0.960s |
36.455us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
keymgr_dpe_csr_rw |
0.800s |
111.528us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
keymgr_dpe_csr_bit_bash |
11.570s |
2.848ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
keymgr_dpe_csr_aliasing |
2.420s |
329.452us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
keymgr_dpe_csr_mem_rw_with_rand_reset |
1.500s |
115.794us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
keymgr_dpe_csr_rw |
0.800s |
111.528us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
2.420s |
329.452us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
intr_test |
keymgr_dpe_intr_test |
0.920s |
76.114us |
1 |
1 |
100.00 |
| V2 |
alert_test |
keymgr_dpe_alert_test |
0.750s |
17.541us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
keymgr_dpe_tl_errors |
1.720s |
209.181us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
keymgr_dpe_tl_errors |
1.720s |
209.181us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
keymgr_dpe_csr_hw_reset |
0.960s |
36.455us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
0.800s |
111.528us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
2.420s |
329.452us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
2.540s |
107.769us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
keymgr_dpe_csr_hw_reset |
0.960s |
36.455us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
0.800s |
111.528us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
2.420s |
329.452us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
2.540s |
107.769us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
4 |
4 |
100.00 |
| V2S |
tl_intg_err |
keymgr_dpe_sec_cm |
17.950s |
1.045ms |
1 |
1 |
100.00 |
|
|
keymgr_dpe_tl_intg_err |
3.530s |
137.530us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error |
keymgr_dpe_shadow_reg_errors |
1.360s |
617.460us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
keymgr_dpe_shadow_reg_errors |
1.360s |
617.460us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
keymgr_dpe_shadow_reg_errors |
1.360s |
617.460us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
keymgr_dpe_shadow_reg_errors |
1.360s |
617.460us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
keymgr_dpe_shadow_reg_errors_with_csr_rw |
1.780s |
194.603us |
1 |
1 |
100.00 |
| V2S |
prim_count_check |
keymgr_dpe_sec_cm |
17.950s |
1.045ms |
1 |
1 |
100.00 |
| V2S |
prim_fsm_check |
keymgr_dpe_sec_cm |
17.950s |
1.045ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
4 |
4 |
100.00 |
|
|
TOTAL |
|
|
14 |
14 |
100.00 |