| V1 |
smoke |
kmac_smoke |
54.680s |
3.701ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
kmac_csr_hw_reset |
1.210s |
14.845us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
kmac_csr_rw |
1.160s |
17.097us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
kmac_csr_bit_bash |
12.650s |
975.478us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
kmac_csr_aliasing |
3.130s |
136.861us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
kmac_csr_mem_rw_with_rand_reset |
1.240s |
45.231us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
kmac_csr_rw |
1.160s |
17.097us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
3.130s |
136.861us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
kmac_mem_walk |
1.040s |
38.054us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
kmac_mem_partial_access |
1.690s |
258.310us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
long_msg_and_output |
kmac_long_msg_and_output |
4.591m |
15.628ms |
1 |
1 |
100.00 |
| V2 |
burst_write |
kmac_burst_write |
2.564m |
14.974ms |
1 |
1 |
100.00 |
| V2 |
test_vectors |
kmac_test_vectors_sha3_224 |
29.050s |
1.316ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_256 |
38.210s |
10.375ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_384 |
26.384m |
138.793ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_512 |
18.770s |
2.995ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_128 |
2.482m |
14.931ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_256 |
28.885m |
57.736ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac |
2.770s |
144.435us |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac_xof |
2.770s |
221.730us |
1 |
1 |
100.00 |
| V2 |
sideload |
kmac_sideload |
5.725m |
14.443ms |
1 |
1 |
100.00 |
| V2 |
app |
kmac_app |
3.448m |
16.938ms |
1 |
1 |
100.00 |
| V2 |
app_with_partial_data |
kmac_app_with_partial_data |
4.782m |
79.924ms |
1 |
1 |
100.00 |
| V2 |
entropy_refresh |
kmac_entropy_refresh |
1.125m |
4.850ms |
1 |
1 |
100.00 |
| V2 |
error |
kmac_error |
4.472m |
13.475ms |
1 |
1 |
100.00 |
| V2 |
key_error |
kmac_key_error |
2.180s |
145.423us |
1 |
1 |
100.00 |
| V2 |
sideload_invalid |
kmac_sideload_invalid |
4.750s |
97.843us |
1 |
1 |
100.00 |
| V2 |
edn_timeout_error |
kmac_edn_timeout_error |
1.230s |
72.535us |
1 |
1 |
100.00 |
| V2 |
entropy_mode_error |
kmac_entropy_mode_error |
0.990s |
57.928us |
1 |
1 |
100.00 |
| V2 |
entropy_ready_error |
kmac_entropy_ready_error |
53.170s |
26.291ms |
1 |
1 |
100.00 |
| V2 |
lc_escalation |
kmac_lc_escalation |
1.610s |
471.625us |
1 |
1 |
100.00 |
| V2 |
stress_all |
kmac_stress_all |
2.250m |
10.068ms |
1 |
1 |
100.00 |
| V2 |
intr_test |
kmac_intr_test |
1.110s |
28.315us |
1 |
1 |
100.00 |
| V2 |
alert_test |
kmac_alert_test |
1.140s |
16.693us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
kmac_tl_errors |
3.010s |
227.490us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
kmac_tl_errors |
3.010s |
227.490us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
kmac_csr_hw_reset |
1.210s |
14.845us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
1.160s |
17.097us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
3.130s |
136.861us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
2.030s |
243.019us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
kmac_csr_hw_reset |
1.210s |
14.845us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
1.160s |
17.097us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
3.130s |
136.861us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
2.030s |
243.019us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
26 |
26 |
100.00 |
| V2S |
shadow_reg_update_error |
kmac_shadow_reg_errors |
1.930s |
284.428us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
kmac_shadow_reg_errors |
1.930s |
284.428us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
kmac_shadow_reg_errors |
1.930s |
284.428us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
kmac_shadow_reg_errors |
1.930s |
284.428us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
kmac_shadow_reg_errors_with_csr_rw |
5.640s |
520.808us |
1 |
1 |
100.00 |
| V2S |
tl_intg_err |
kmac_sec_cm |
43.390s |
3.822ms |
1 |
1 |
100.00 |
|
|
kmac_tl_intg_err |
2.860s |
198.538us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
kmac_tl_intg_err |
2.860s |
198.538us |
1 |
1 |
100.00 |
| V2S |
sec_cm_lc_escalate_en_intersig_mubi |
kmac_lc_escalation |
1.610s |
471.625us |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_key_key_masking |
kmac_smoke |
54.680s |
3.701ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_key_sideload |
kmac_sideload |
5.725m |
14.443ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_shadow |
kmac_shadow_reg_errors |
1.930s |
284.428us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_sparse |
kmac_sec_cm |
43.390s |
3.822ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_ctr_redun |
kmac_sec_cm |
43.390s |
3.822ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_packer_ctr_redun |
kmac_sec_cm |
43.390s |
3.822ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_regwen |
kmac_smoke |
54.680s |
3.701ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_global_esc |
kmac_lc_escalation |
1.610s |
471.625us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_local_esc |
kmac_sec_cm |
43.390s |
3.822ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_absorbed_ctrl_mubi |
kmac_mubi |
1.111m |
3.124ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_cmd_ctrl_sparse |
kmac_smoke |
54.680s |
3.701ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
5 |
5 |
100.00 |
| V3 |
stress_all_with_rand_reset |
kmac_stress_all_with_rand_reset |
1.210m |
5.920ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
40 |
40 |
100.00 |