KMAC/UNMASKED Simulation Results

Thursday October 09 2025 16:09:14 UTC

GitHub Revision: 677ee3d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	27.300s	4.653ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.790s	19.008us	1	1	100.00
V1	csr_rw	kmac_csr_rw	0.980s	78.191us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.150s	1.433ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.330s	1.581ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.050s	307.998us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.980s	78.191us	1	1	100.00
		kmac_csr_aliasing	6.330s	1.581ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.800s	114.591us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.200s	84.930us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	14.838m	585.108ms	1	1	100.00
V2	burst_write	kmac_burst_write	7.896m	55.263ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	20.321m	23.578ms	1	1	100.00
		kmac_test_vectors_sha3_256	18.912m	75.644ms	1	1	100.00
		kmac_test_vectors_sha3_384	19.420s	2.322ms	1	1	100.00
		kmac_test_vectors_sha3_512	13.170s	2.878ms	1	1	100.00
		kmac_test_vectors_shake_128	2.757m	13.871ms	1	1	100.00
		kmac_test_vectors_shake_256	18.863m	34.052ms	1	1	100.00
		kmac_test_vectors_kmac	1.650s	356.457us	1	1	100.00
		kmac_test_vectors_kmac_xof	1.740s	95.547us	1	1	100.00
V2	sideload	kmac_sideload	3.409m	43.155ms	1	1	100.00
V2	app	kmac_app	42.180s	6.576ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.030s	650.711us	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.110m	14.810ms	1	1	100.00
V2	error	kmac_error	42.400s	21.484ms	1	1	100.00
V2	key_error	kmac_key_error	2.460s	196.867us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.250s	971.313us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	13.820s	945.592us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	15.610s	607.241us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	20.230s	11.364ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.530s	107.301us	1	1	100.00
V2	stress_all	kmac_stress_all	6.034m	12.736ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.800s	37.663us	1	1	100.00
V2	alert_test	kmac_alert_test	0.920s	17.859us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	1.280s	46.300us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	1.280s	46.300us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.790s	19.008us	1	1	100.00
		kmac_csr_rw	0.980s	78.191us	1	1	100.00
		kmac_csr_aliasing	6.330s	1.581ms	1	1	100.00
		kmac_same_csr_outstanding	1.450s	125.308us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.790s	19.008us	1	1	100.00
		kmac_csr_rw	0.980s	78.191us	1	1	100.00
		kmac_csr_aliasing	6.330s	1.581ms	1	1	100.00
		kmac_same_csr_outstanding	1.450s	125.308us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.830s	120.114us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.830s	120.114us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.830s	120.114us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.830s	120.114us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.090s	289.405us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	44.030s	5.873ms	1	1	100.00
		kmac_tl_intg_err	3.120s	504.305us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.120s	504.305us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.530s	107.301us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	27.300s	4.653ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.409m	43.155ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.830s	120.114us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	44.030s	5.873ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	44.030s	5.873ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	44.030s	5.873ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	27.300s	4.653ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.530s	107.301us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	44.030s	5.873ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.936m	3.964ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	27.300s	4.653ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	29.040s	1.402ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.54780377546303304857143975557082174582451549097521046846885397506417882474433
      Line 125, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1402248496 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1402248496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---