MBX Simulation Results

Thursday October 09 2025 16:09:14 UTC

GitHub Revision: 677ee3d

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 mbx_smoke mbx_smoke 21.000s 7.698ms 1 1 100.00
V1 csr_hw_reset mbx_csr_hw_reset 2.000s 13.509us 1 1 100.00
V1 csr_rw mbx_csr_rw 2.000s 66.857us 1 1 100.00
V1 csr_bit_bash mbx_csr_bit_bash 4.000s 323.659us 1 1 100.00
V1 csr_aliasing mbx_csr_aliasing 2.000s 128.092us 1 1 100.00
V1 csr_mem_rw_with_rand_reset mbx_csr_mem_rw_with_rand_reset 2.000s 40.977us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr mbx_csr_rw 2.000s 66.857us 1 1 100.00
mbx_csr_aliasing 2.000s 128.092us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 mbx_stress mbx_stress 13.000s 1.093ms 0 1 0.00
V2 mbx_max_activity mbx_stress_zero_delays 1.767m 12.852ms 1 1 100.00
V2 mbx_imbx_oob mbx_imbx_oob 33.000s 1.634ms 1 1 100.00
V2 mbx_doe_intr_msg mbx_doe_intr_msg 10.000s 2.573ms 1 1 100.00
V2 alert_test mbx_alert_test 1.000s 51.373us 1 1 100.00
V2 intr_test mbx_intr_test 1.000s 42.435us 1 1 100.00
V2 tl_d_oob_addr_access mbx_tl_errors 2.000s 168.016us 1 1 100.00
V2 tl_d_illegal_access mbx_tl_errors 2.000s 168.016us 1 1 100.00
V2 tl_d_outstanding_access mbx_csr_hw_reset 2.000s 13.509us 1 1 100.00
mbx_csr_rw 2.000s 66.857us 1 1 100.00
mbx_csr_aliasing 2.000s 128.092us 1 1 100.00
mbx_same_csr_outstanding 2.000s 175.596us 1 1 100.00
V2 tl_d_partial_access mbx_csr_hw_reset 2.000s 13.509us 1 1 100.00
mbx_csr_rw 2.000s 66.857us 1 1 100.00
mbx_csr_aliasing 2.000s 128.092us 1 1 100.00
mbx_same_csr_outstanding 2.000s 175.596us 1 1 100.00
V2 TOTAL 7 8 87.50
V2S tl_intg_err mbx_tl_intg_err 2.000s 75.038us 1 1 100.00
mbx_sec_cm 1.000s 19.584us 1 1 100.00
V2S TOTAL 2 2 100.00
TOTAL 15 16 93.75

Failure Buckets