OTBN Simulation Results

Thursday October 09 2025 16:09:14 UTC

GitHub Revision: 677ee3d

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 9.000s 37.502us 0 1 0.00
V1 single_binary otbn_single 5.000s 19.490us 0 1 0.00
V1 csr_hw_reset otbn_csr_hw_reset 4.000s 19.688us 1 1 100.00
V1 csr_rw otbn_csr_rw 3.000s 67.263us 1 1 100.00
V1 csr_bit_bash otbn_csr_bit_bash 6.000s 176.269us 1 1 100.00
V1 csr_aliasing otbn_csr_aliasing 3.000s 51.129us 1 1 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 5.000s 35.035us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 3.000s 67.263us 1 1 100.00
otbn_csr_aliasing 3.000s 51.129us 1 1 100.00
V1 mem_walk otbn_mem_walk 17.000s 2.532ms 1 1 100.00
V1 mem_partial_access otbn_mem_partial_access 13.000s 731.785us 1 1 100.00
V1 TOTAL 7 9 77.78
V2 reset_recovery otbn_reset 31.000s 186.557us 0 1 0.00
V2 multi_error otbn_multi_err 40.000s 161.146us 0 1 0.00
V2 back_to_back otbn_multi 33.000s 158.385us 0 1 0.00
V2 stress_all otbn_stress_all 1.167m 400.722us 0 1 0.00
V2 lc_escalation otbn_escalate 7.000s 18.655us 0 1 0.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 4.000s 29.196us 1 1 100.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 9.000s 36.288us 0 1 0.00
V2 alert_test otbn_alert_test 5.000s 20.787us 1 1 100.00
V2 intr_test otbn_intr_test 3.000s 20.491us 1 1 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 4.000s 79.761us 1 1 100.00
V2 tl_d_illegal_access otbn_tl_errors 4.000s 79.761us 1 1 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 4.000s 19.688us 1 1 100.00
otbn_csr_rw 3.000s 67.263us 1 1 100.00
otbn_csr_aliasing 3.000s 51.129us 1 1 100.00
otbn_same_csr_outstanding 3.000s 52.486us 1 1 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 4.000s 19.688us 1 1 100.00
otbn_csr_rw 3.000s 67.263us 1 1 100.00
otbn_csr_aliasing 3.000s 51.129us 1 1 100.00
otbn_same_csr_outstanding 3.000s 52.486us 1 1 100.00
V2 TOTAL 5 11 45.45
V2S mem_integrity otbn_imem_err 8.000s 17.159us 0 1 0.00
otbn_dmem_err 6.000s 118.169us 0 1 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 6.000s 58.463us 0 1 0.00
otbn_controller_ispr_rdata_err 11.000s 75.088us 0 1 0.00
otbn_mac_bignum_acc_err 6.000s 45.716us 0 1 0.00
otbn_urnd_err 4.000s 29.348us 1 1 100.00
V2S illegal_bus_access otbn_illegal_mem_acc 4.000s 68.930us 1 1 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 5.000s 12.752us 1 1 100.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 5.000s 18.757us 1 1 100.00
V2S tl_intg_err otbn_sec_cm 2.950m 5.293ms 1 1 100.00
otbn_tl_intg_err 17.000s 2.565ms 1 1 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 20.000s 348.627us 1 1 100.00
V2S prim_fsm_check otbn_sec_cm 2.950m 5.293ms 1 1 100.00
V2S prim_count_check otbn_sec_cm 2.950m 5.293ms 1 1 100.00
V2S sec_cm_mem_scramble otbn_smoke 9.000s 37.502us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 6.000s 118.169us 0 1 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 8.000s 17.159us 0 1 0.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 17.000s 2.565ms 1 1 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 7.000s 18.655us 0 1 0.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 8.000s 17.159us 0 1 0.00
otbn_dmem_err 6.000s 118.169us 0 1 0.00
otbn_zero_state_err_urnd 4.000s 29.196us 1 1 100.00
otbn_illegal_mem_acc 4.000s 68.930us 1 1 100.00
otbn_sec_cm 2.950m 5.293ms 1 1 100.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 2.950m 5.293ms 1 1 100.00
V2S sec_cm_scramble_key_sideload otbn_single 5.000s 19.490us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 8.000s 17.159us 0 1 0.00
otbn_dmem_err 6.000s 118.169us 0 1 0.00
otbn_zero_state_err_urnd 4.000s 29.196us 1 1 100.00
otbn_illegal_mem_acc 4.000s 68.930us 1 1 100.00
otbn_sec_cm 2.950m 5.293ms 1 1 100.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 2.950m 5.293ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 7.000s 18.655us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 8.000s 17.159us 0 1 0.00
otbn_dmem_err 6.000s 118.169us 0 1 0.00
otbn_zero_state_err_urnd 4.000s 29.196us 1 1 100.00
otbn_illegal_mem_acc 4.000s 68.930us 1 1 100.00
otbn_sec_cm 2.950m 5.293ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 2.950m 5.293ms 1 1 100.00
V2S sec_cm_data_reg_sw_sca otbn_single 5.000s 19.490us 0 1 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 6.000s 20.489us 0 1 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 5.000s 81.386us 1 1 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 29.000s 145.296us 0 1 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 29.000s 145.296us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 19.000s 81.807us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 2.950m 5.293ms 1 1 100.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 2.950m 5.293ms 1 1 100.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 6.000s 38.540us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 2.950m 5.293ms 1 1 100.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 2.950m 5.293ms 1 1 100.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 6.000s 54.643us 0 1 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 6.000s 54.643us 0 1 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 4.000s 28.622us 1 1 100.00
V2S sec_cm_data_mem_sec_wipe otbn_single 5.000s 19.490us 0 1 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 5.000s 19.490us 0 1 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 5.000s 19.490us 0 1 0.00
V2S sec_cm_write_mem_integrity otbn_multi 33.000s 158.385us 0 1 0.00
V2S sec_cm_ctrl_flow_count otbn_single 5.000s 19.490us 0 1 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 5.000s 19.490us 0 1 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 6.000s 41.058us 0 1 0.00
V2S sec_cm_key_sideload otbn_single 5.000s 19.490us 0 1 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 2.950m 5.293ms 1 1 100.00
V2S TOTAL 9 20 45.00
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 6.367m 7.300ms 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 21 41 51.22

Failure Buckets