677ee3d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 2.370s | 1.838ms | 1 | 1 | 100.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 1.330s | 571.790us | 1 | 1 | 100.00 |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 0.820s | 349.666us | 1 | 1 | 100.00 |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 7.150s | 9.567ms | 1 | 1 | 100.00 |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 1.170s | 771.499us | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 2.110s | 1.501ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 4.170s | 2.061ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 4.980s | 10.672ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 45.790s | 26.005ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 1.030s | 241.365us | 1 | 1 | 100.00 |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 1.130s | 253.978us | 1 | 1 | 100.00 |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 0.820s | 169.081us | 1 | 1 | 100.00 |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 0.620s | 66.382us | 0 | 1 | 0.00 |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 0.990s | 562.216us | 1 | 1 | 100.00 |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 0.950s | 160.801us | 1 | 1 | 100.00 |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 0.780s | 55.144us | 1 | 1 | 100.00 |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 0.850s | 859.475us | 1 | 1 | 100.00 |
| V1 | progbuf_busy | rv_dm_cmderr_busy | 1.030s | 241.365us | 1 | 1 | 100.00 |
| V1 | abstractcmd_status | rv_dm_abstractcmd_status | 0.850s | 281.499us | 1 | 1 | 100.00 |
| V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 1.980s | 1.303ms | 1 | 1 | 100.00 |
| V1 | progbuf_exception | rv_dm_cmderr_exception | 0.820s | 169.081us | 1 | 1 | 100.00 |
| V1 | rom_read_access | rv_dm_rom_read_access | 0.760s | 27.663us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 1.950s | 212.788us | 1 | 1 | 100.00 |
| V1 | csr_rw | rv_dm_csr_rw | 1.890s | 174.129us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 25.430s | 19.211ms | 1 | 1 | 100.00 |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 47.640s | 3.462ms | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 0.710s | 124.427us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 47.640s | 3.462ms | 1 | 1 | 100.00 |
| rv_dm_csr_rw | 1.890s | 174.129us | 1 | 1 | 100.00 | ||
| V1 | mem_walk | rv_dm_mem_walk | 0.770s | 78.793us | 1 | 1 | 100.00 |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 0.700s | 45.041us | 1 | 1 | 100.00 |
| V1 | TOTAL | 25 | 27 | 92.59 | |||
| V2 | idcode | rv_dm_smoke | 2.370s | 1.838ms | 1 | 1 | 100.00 |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 1.530s | 537.941us | 1 | 1 | 100.00 |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 0.770s | 150.973us | 1 | 1 | 100.00 |
| V2 | jtag_dmi_failed_op | rv_dm_dmi_failed_op | 0.880s | 347.247us | 1 | 1 | 100.00 |
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 1.380s | 683.872us | 1 | 1 | 100.00 |
| V2 | sba | rv_dm_sba_tl_access | 5.220m | 300.000ms | 0 | 1 | 0.00 |
| rv_dm_delayed_resp_sba_tl_access | 1.883m | 300.000ms | 0 | 1 | 0.00 | ||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 8.912m | 300.000ms | 0 | 1 | 0.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 2.343m | 300.000ms | 0 | 1 | 0.00 |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 1.280s | 350.853us | 0 | 1 | 0.00 |
| V2 | sba_debug_disabled | rv_dm_sba_debug_disabled | 3.330s | 1.564ms | 1 | 1 | 100.00 |
| V2 | ndmreset_req | rv_dm_ndmreset_req | 0.760s | 383.945us | 1 | 1 | 100.00 |
| V2 | hart_unavail | rv_dm_hart_unavail | 1.090s | 423.717us | 0 | 1 | 0.00 |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 20.430s | 11.301ms | 1 | 1 | 100.00 |
| rv_dm_tap_fsm_rand_reset | 0.990s | 110.471us | 0 | 1 | 0.00 | ||
| V2 | hartsel_warl | rv_dm_hartsel_warl | 0.670s | 105.743us | 1 | 1 | 100.00 |
| V2 | stress_all | rv_dm_stress_all | 1.380s | 758.697us | 0 | 1 | 0.00 |
| V2 | alert_test | rv_dm_alert_test | 0.710s | 58.074us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 0.750s | 60.731us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 0.750s | 60.731us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 47.640s | 3.462ms | 1 | 1 | 100.00 |
| rv_dm_csr_hw_reset | 1.950s | 212.788us | 1 | 1 | 100.00 | ||
| rv_dm_csr_rw | 1.890s | 174.129us | 1 | 1 | 100.00 | ||
| rv_dm_same_csr_outstanding | 5.630s | 902.045us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 47.640s | 3.462ms | 1 | 1 | 100.00 |
| rv_dm_csr_hw_reset | 1.950s | 212.788us | 1 | 1 | 100.00 | ||
| rv_dm_csr_rw | 1.890s | 174.129us | 1 | 1 | 100.00 | ||
| rv_dm_same_csr_outstanding | 5.630s | 902.045us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 10 | 19 | 52.63 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 1.250s | 290.863us | 1 | 1 | 100.00 |
| rv_dm_tl_intg_err | 12.660s | 6.706ms | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_dm_tl_intg_err | 12.660s | 6.706ms | 1 | 1 | 100.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | rv_dm_sba_debug_disabled | 3.330s | 1.564ms | 1 | 1 | 100.00 |
| rv_dm_debug_disabled | 0.830s | 45.680us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_lc_dft_en_intersig_mubi | rv_dm_sba_debug_disabled | 3.330s | 1.564ms | 1 | 1 | 100.00 |
| rv_dm_debug_disabled | 0.830s | 45.680us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | rv_dm_smoke | 2.370s | 1.838ms | 1 | 1 | 100.00 |
| V2S | sec_cm_dm_en_ctrl_lc_gated | rv_dm_buffered_enable | 0.890s | 97.046us | 1 | 1 | 100.00 |
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 0.780s | 213.266us | 1 | 1 | 100.00 |
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 0.780s | 213.266us | 1 | 1 | 100.00 |
| V2S | sec_cm_exec_ctrl_mubi | rv_dm_buffered_enable | 0.890s | 97.046us | 1 | 1 | 100.00 |
| V2S | TOTAL | 5 | 5 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 0.650s | 24.529us | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| Unmapped tests | rv_dm_scanmode | 2.282m | 300.000ms | 0 | 1 | 0.00 | |
| TOTAL | 40 | 53 | 75.47 |
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 5 failures:
Test rv_dm_sba_tl_access has 1 failures.
0.rv_dm_sba_tl_access.22232180780051093261922227412874070406353200648027290101954534819717383911384
Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_delayed_resp_sba_tl_access has 1 failures.
0.rv_dm_delayed_resp_sba_tl_access.90609097042341977310115181107811472233912758204206147992423494487298343630606
Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_bad_sba_tl_access has 1 failures.
0.rv_dm_bad_sba_tl_access.44071937679619549480596798890954099966672982045545422698867260499652051191396
Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_autoincr_sba_tl_access has 1 failures.
0.rv_dm_autoincr_sba_tl_access.9428644617052326187860729505946131282352163131844099860683948634650109777251
Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_scanmode has 1 failures.
0.rv_dm_scanmode.30754642962631752921781326287258749748925051016236047103220384092886704040063
Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_scanmode/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 2 failures:
Test rv_dm_jtag_dmi_debug_disabled has 1 failures.
0.rv_dm_jtag_dmi_debug_disabled.49770393248821582992398237689471348398038551095892903439835821921933882054510
Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest/run.log
UVM_ERROR @ 350852958 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (211003936 [0xc93aa20] vs 0 [0x0])
UVM_INFO @ 350852958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 1 failures.
0.rv_dm_stress_all.40452881607243428652349910871450378270410634301891541024263041551151025526773
Line 75, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 758696941 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (20955876 [0x13fc2e4] vs 0 [0x0])
UVM_INFO @ 758696941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@8406) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_tap_fsm_rand_reset.28928873824161097649761058995947588322302987068258329353505768665510246233832
Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 110470806 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@8406) { a_addr: 'hc5bdf590 a_data: 'h69209bf0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h30 a_opcode: 'h4 a_user: 'h1a09a d_param: 'h0 d_source: 'h30 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 110470806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed gmv(jtag_dmi_ral.dmstatus.anyhalted) == 'b (* [] vs * [])` has 1 failures:
0.rv_dm_mem_tl_access_resuming.62608704769641827313043728617706017684034846154584304870015117971193636187596
Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_resuming/latest/run.log
UVM_ERROR @ 66381610 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 66381610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [] vs * [])` has 1 failures:
0.rv_dm_hart_unavail.54029214092909630344619219902620251435462895856014166724798293270256397677441
Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_hart_unavail/latest/run.log
UVM_ERROR @ 423717234 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 423717234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5634) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_stress_all_with_rand_reset.44808235213327652222066114407841198767743480593972055869650422693644284585593
Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 24528806 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5634) { a_addr: 'h9fba2668 a_data: 'hca665237 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h6d a_opcode: 'h4 a_user: 'h1876d d_param: 'h0 d_source: 'h6d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 24528806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5796) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_tl_errors.109704307321310456326084041833193405579485291938093960672329956607983663982488
Line 75, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tl_errors/latest/run.log
UVM_ERROR @ 60730927 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5796) { a_addr: 'ha8b2a4a8 a_data: 'h390dc30d a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1c a_opcode: 'h4 a_user: 'h18746 d_param: 'h0 d_source: 'h1c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 60730927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5564) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_csr_mem_rw_with_rand_reset.68740425006314779388470348273501357741503075917538856352766139230042503401322
Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 124427200 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5564) { a_addr: 'hadc78464 a_data: 'h693d3702 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hb0 a_opcode: 'h4 a_user: 'h18b0c d_param: 'h0 d_source: 'hb0 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 124427200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---