RV_TIMER Simulation Results

Thursday October 09 2025 16:09:14 UTC

GitHub Revision: 677ee3d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	0.790s	411.323us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.760s	34.001us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.670s	44.678us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.000s	1.946ms	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.770s	36.583us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	0.740s	18.201us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.670s	44.678us	1	1	100.00
		rv_timer_csr_aliasing	0.770s	36.583us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	0.720s	84.891us	0	1	0.00
V2	disabled	rv_timer_disabled	1.010s	2.916ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	3.083m	521.911ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	3.083m	521.911ms	1	1	100.00
V2	stress	rv_timer_stress_all	2.960s	2.107ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.570s	21.926us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.630s	72.865us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.340s	173.447us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.340s	173.447us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.760s	34.001us	1	1	100.00
		rv_timer_csr_rw	0.670s	44.678us	1	1	100.00
		rv_timer_csr_aliasing	0.770s	36.583us	1	1	100.00
		rv_timer_same_csr_outstanding	0.880s	30.660us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.760s	34.001us	1	1	100.00
		rv_timer_csr_rw	0.670s	44.678us	1	1	100.00
		rv_timer_csr_aliasing	0.770s	36.583us	1	1	100.00
		rv_timer_same_csr_outstanding	0.880s	30.660us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	rv_timer_sec_cm	0.720s	336.687us	1	1	100.00
		rv_timer_tl_intg_err	0.740s	52.143us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	0.740s	52.143us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	1.850s	217.087us	0	1	0.00
V3	max_value	rv_timer_max	0.600s	45.921us	0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	10.620s	6.627ms	1	1	100.00
V3		TOTAL			1	3	33.33
		TOTAL			16	19	84.21

Failure Buckets

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:

  • Test rv_timer_min has 1 failures.

    • 0.rv_timer_min.100751609465178340971309800637416637663401369729329266552485612327293547874353
      Line 74, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log

        UVM_FATAL @ 217087127 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xab50b04) == 0x1
        UVM_INFO @ 217087127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.97885503855522497408349981427620598208569325595679844580107866047856574703068
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @  84891177 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xc8898704) == 0x1
        UVM_INFO @  84891177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.83416151542589136161058212581626335835483790295641593707847943198049706048754
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @  45921191 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @  45921191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---