SPI_DEVICE/1R1W Simulation Results

Thursday October 09 2025 16:09:14 UTC

GitHub Revision: 677ee3d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	3.001m	522.465ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.420s	460.779us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.080s	85.456us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	23.010s	2.088ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	4.860s	113.882us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.080s	97.439us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.080s	85.456us	1	1	100.00
		spi_device_csr_aliasing	4.860s	113.882us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.670s	11.040us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.270s	103.652us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.950s	23.357us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.900s	1.688us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.750s	15.960us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.880s	433.829us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.880s	433.829us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	7.120s	9.635ms	1	1	100.00
		spi_device_tpm_sts_read	0.970s	48.219us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	13.330s	4.420ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	1.910s	825.405us	1	1	100.00
		spi_device_flash_all	20.470s	17.713ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	13.550s	12.518ms	1	1	100.00
		spi_device_flash_all	20.470s	17.713ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	13.550s	12.518ms	1	1	100.00
		spi_device_flash_all	20.470s	17.713ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	20.470s	17.713ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.680s	337.285us	1	1	100.00
		spi_device_flash_all	20.470s	17.713ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.680s	337.285us	1	1	100.00
		spi_device_flash_all	20.470s	17.713ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.680s	337.285us	1	1	100.00
		spi_device_flash_all	20.470s	17.713ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.680s	337.285us	1	1	100.00
		spi_device_flash_all	20.470s	17.713ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.680s	337.285us	1	1	100.00
		spi_device_flash_all	20.470s	17.713ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	7.190s	6.028ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	1.067m	8.998ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.067m	8.998ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.067m	8.998ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	6.770s	379.193us	1	1	100.00
		spi_device_read_buffer_direct	3.470s	456.281us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.067m	8.998ms	1	1	100.00
		spi_device_flash_all	20.470s	17.713ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	20.470s	17.713ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	20.470s	17.713ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.550s	58.416us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.550s	58.416us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	3.001m	522.465ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	3.124m	115.238ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.180s	47.689us	1	1	100.00
V2	alert_test	spi_device_alert_test	0.890s	28.206us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.730s	50.914us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	1.600s	205.750us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	1.600s	205.750us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.420s	460.779us	1	1	100.00
		spi_device_csr_rw	2.080s	85.456us	1	1	100.00
		spi_device_csr_aliasing	4.860s	113.882us	1	1	100.00
		spi_device_same_csr_outstanding	2.240s	149.514us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.420s	460.779us	1	1	100.00
		spi_device_csr_rw	2.080s	85.456us	1	1	100.00
		spi_device_csr_aliasing	4.860s	113.882us	1	1	100.00
		spi_device_same_csr_outstanding	2.240s	149.514us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.340s	374.178us	1	1	100.00
		spi_device_tl_intg_err	10.300s	550.543us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	10.300s	550.543us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	2.418m	22.866ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.80241619417364985213077433287634340007625833843226217200591053912301301255545
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1021331 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[12])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1021331 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1021331 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[908])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.95655441565192258869875139812416450504553434394906379624703727526658811908280
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @  13432642 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb319ab [101100110001100110101011] vs 0x0 [0])
        UVM_ERROR @  13457642 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x19197b [110010001100101111011] vs 0x0 [0])
        UVM_ERROR @  13556642 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x355f1 [110101010111110001] vs 0x0 [0])
        UVM_ERROR @  13614642 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf7a45f [111101111010010001011111] vs 0x0 [0])
        UVM_ERROR @  13700642 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x39adc3 [1110011010110111000011] vs 0x0 [0])