SPI_HOST Simulation Results

Thursday October 09 2025 16:09:14 UTC

GitHub Revision: 677ee3d

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	11.000s	777.405us	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	134.745us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	18.996us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	2.000s	764.624us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	1.000s	23.428us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	1.000s	27.024us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	18.996us	1	1	100.00
		spi_host_csr_aliasing	1.000s	23.428us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	52.842us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	52.620us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	2.000s	19.543us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	4.000s	159.105us	1	1	100.00
		spi_host_error_cmd	1.000s	15.456us	1	1	100.00
		spi_host_event	28.000s	3.786ms	1	1	100.00
V2	clock_rate	spi_host_speed	2.000s	44.652us	1	1	100.00
V2	speed	spi_host_speed	2.000s	44.652us	1	1	100.00
V2	chip_select_timing	spi_host_speed	2.000s	44.652us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	5.000s	217.367us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	2.000s	144.662us	1	1	100.00
V2	cpol_cpha	spi_host_speed	2.000s	44.652us	1	1	100.00
V2	full_cycle	spi_host_speed	2.000s	44.652us	1	1	100.00
V2	duplex	spi_host_smoke	11.000s	777.405us	1	1	100.00
V2	tx_rx_only	spi_host_smoke	11.000s	777.405us	1	1	100.00
V2	stress_all	spi_host_stress_all	5.000s	903.188us	1	1	100.00
V2	spien	spi_host_spien	5.000s	463.769us	1	1	100.00
V2	stall	spi_host_status_stall	48.000s	5.449ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	2.000s	45.810us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	4.000s	159.105us	1	1	100.00
V2	alert_test	spi_host_alert_test	1.000s	23.833us	1	1	100.00
V2	intr_test	spi_host_intr_test	6.000s	18.516us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	10.000s	73.516us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	10.000s	73.516us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	134.745us	1	1	100.00
		spi_host_csr_rw	2.000s	18.996us	1	1	100.00
		spi_host_csr_aliasing	1.000s	23.428us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	77.093us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	134.745us	1	1	100.00
		spi_host_csr_rw	2.000s	18.996us	1	1	100.00
		spi_host_csr_aliasing	1.000s	23.428us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	77.093us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	8.000s	150.784us	1	1	100.00
		spi_host_sec_cm	2.000s	151.635us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	8.000s	150.784us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	2.250m	5.008ms	1	1	100.00
		TOTAL			26	26	100.00