SRAM_CTRL/MAIN Simulation Results

Thursday October 09 2025 16:09:14 UTC

GitHub Revision: 677ee3d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	12.740s	3.313ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.910s	22.260us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.650s	37.288us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.120s	242.445us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.710s	85.435us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.520s	364.814us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.650s	37.288us	1	1	100.00
		sram_ctrl_csr_aliasing	0.710s	85.435us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.722m	5.256ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.578m	6.287ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	11.070s	1.211ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	1.936m	11.501ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	29.190m	33.217ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	11.740m	16.352ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	49.060s	46.236ms	1	1	100.00
V2	executable	sram_ctrl_executable	15.594m	62.487ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	16.830s	1.004ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.480m	9.302ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	3.910s	716.665us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	33.570s	4.262ms	1	1	100.00
		sram_ctrl_throughput_w_readback	35.850s	1.921ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	10.815m	4.216ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.470s	695.199us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	49.163m	418.740ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.790s	30.032us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.400s	92.814us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.400s	92.814us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.910s	22.260us	1	1	100.00
		sram_ctrl_csr_rw	0.650s	37.288us	1	1	100.00
		sram_ctrl_csr_aliasing	0.710s	85.435us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.730s	33.412us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.910s	22.260us	1	1	100.00
		sram_ctrl_csr_rw	0.650s	37.288us	1	1	100.00
		sram_ctrl_csr_aliasing	0.710s	85.435us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.730s	33.412us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	31.940s	7.370ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.880s	1.929us	0	1	0.00
		sram_ctrl_tl_intg_err	1.980s	463.881us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.880s	1.929us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.980s	463.881us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	10.815m	4.216ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	10.815m	4.216ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.650s	37.288us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	15.594m	62.487ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	15.594m	62.487ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	15.594m	62.487ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	49.060s	46.236ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.120s	663.715us	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	31.940s	7.370ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	7.020s	864.516us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	12.740s	3.313ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	12.740s	3.313ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	15.594m	62.487ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.880s	1.929us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	49.060s	46.236ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.880s	1.929us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.880s	1.929us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	12.740s	3.313ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.880s	1.929us	0	1	0.00
V2S		TOTAL			2	5	40.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	6.940s	265.200us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			28	31	90.32

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.1517718474637597976481731168658173321596853776184879565519793774393022180158
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 864516136 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x31) != exp (0x1c)
        UVM_INFO @ 864516136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.54207686316845641436013615864613306661813050758151198723735624922643141156859
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 663715105 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 663715105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.59772243803291863946828507139888165507374111935434292234068723133646539036279
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   1928790 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   1928790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---