SRAM_CTRL/RET Simulation Results

Thursday October 09 2025 16:09:14 UTC

GitHub Revision: 677ee3d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	7.210s	1.051ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.870s	17.111us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.800s	32.706us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.470s	59.725us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.800s	58.300us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.070s	35.075us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.800s	32.706us	1	1	100.00
		sram_ctrl_csr_aliasing	0.800s	58.300us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.290s	1.444ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.870s	100.105us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	1.807m	3.551ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.276m	11.461ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	43.690s	10.559ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	4.674m	4.130ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.410s	704.081us	1	1	100.00
V2	executable	sram_ctrl_executable	6.025m	2.386ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	43.570s	203.544us	1	1	100.00
		sram_ctrl_partial_access_b2b	4.417m	36.567ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	7.390s	70.396us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	13.760s	385.702us	1	1	100.00
		sram_ctrl_throughput_w_readback	25.850s	220.284us	1	1	100.00
V2	regwen	sram_ctrl_regwen	10.941m	5.367ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.990s	28.542us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	23.385m	69.673ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.900s	21.618us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	1.930s	23.261us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	1.930s	23.261us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.870s	17.111us	1	1	100.00
		sram_ctrl_csr_rw	0.800s	32.706us	1	1	100.00
		sram_ctrl_csr_aliasing	0.800s	58.300us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.680s	14.742us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.870s	17.111us	1	1	100.00
		sram_ctrl_csr_rw	0.800s	32.706us	1	1	100.00
		sram_ctrl_csr_aliasing	0.800s	58.300us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.680s	14.742us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.600s	586.718us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.890s	15.903us	0	1	0.00
		sram_ctrl_tl_intg_err	2.110s	670.478us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.890s	15.903us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.110s	670.478us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	10.941m	5.367ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	10.941m	5.367ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.800s	32.706us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	6.025m	2.386ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	6.025m	2.386ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	6.025m	2.386ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.410s	704.081us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.020s	183.702us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.600s	586.718us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	0.890s	106.530us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	7.210s	1.051ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	7.210s	1.051ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	6.025m	2.386ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.890s	15.903us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.410s	704.081us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.890s	15.903us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.890s	15.903us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	7.210s	1.051ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.890s	15.903us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	16.620s	665.942us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.6505875781661866782735224068694394118404182630254318729454671777048564960977
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 106529793 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5b) != exp (0xd)
        UVM_INFO @ 106529793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.63361598757166034103537985153849599801490543142935426724874412073444188943837
      Line 99, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  15902550 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  15902550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---