UART Simulation Results

Thursday October 09 2025 16:09:14 UTC

GitHub Revision: 677ee3d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.660s	456.194us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.590s	23.075us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.750s	38.095us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.230s	260.754us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.700s	16.324us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.750s	292.228us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.750s	38.095us	1	1	100.00
		uart_csr_aliasing	0.700s	16.324us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	51.480s	29.550ms	1	1	100.00
V2	parity	uart_smoke	1.660s	456.194us	1	1	100.00
		uart_tx_rx	51.480s	29.550ms	1	1	100.00
V2	parity_error	uart_intr	8.220s	47.547ms	1	1	100.00
		uart_rx_parity_err	2.000m	117.928ms	1	1	100.00
V2	watermark	uart_tx_rx	51.480s	29.550ms	1	1	100.00
		uart_intr	8.220s	47.547ms	1	1	100.00
V2	fifo_full	uart_fifo_full	1.194m	136.677ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	1.523m	94.146ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	23.610s	59.840ms	1	1	100.00
V2	rx_frame_err	uart_intr	8.220s	47.547ms	1	1	100.00
V2	rx_break_err	uart_intr	8.220s	47.547ms	1	1	100.00
V2	rx_timeout	uart_intr	8.220s	47.547ms	1	1	100.00
V2	perf	uart_perf	6.596m	20.170ms	1	1	100.00
V2	sys_loopback	uart_loopback	2.710s	6.281ms	1	1	100.00
V2	line_loopback	uart_loopback	2.710s	6.281ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	1.530s	2.991ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	59.790s	52.095ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	1.870s	1.543ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	22.860s	6.973ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	6.717m	109.661ms	1	1	100.00
V2	stress_all	uart_stress_all	1.864m	30.264ms	1	1	100.00
V2	alert_test	uart_alert_test	0.850s	23.349us	1	1	100.00
V2	intr_test	uart_intr_test	0.670s	38.258us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.180s	24.837us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.180s	24.837us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.590s	23.075us	1	1	100.00
		uart_csr_rw	0.750s	38.095us	1	1	100.00
		uart_csr_aliasing	0.700s	16.324us	1	1	100.00
		uart_same_csr_outstanding	0.770s	37.761us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.590s	23.075us	1	1	100.00
		uart_csr_rw	0.750s	38.095us	1	1	100.00
		uart_csr_aliasing	0.700s	16.324us	1	1	100.00
		uart_same_csr_outstanding	0.770s	37.761us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.170s	62.121us	1	1	100.00
		uart_tl_intg_err	1.250s	86.712us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.250s	86.712us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	22.480s	2.030ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.77716547391195054306083323477031861164273566618034419175129461280126241640816
      Line 72, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 1849261387 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 5,                                 clk_pulses: 0
        UVM_ERROR @ 1849301387 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 1849341387 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 1849381387 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 1849421387 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata