CHIP Simulation Results

Thursday October 09 2025 16:09:14 UTC

GitHub Revision: `677ee3d`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.718m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.718m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	16.828s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	14.930s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	13.803s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	8.078m	6.110ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	8.078m	6.110ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	8.078m	6.110ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	30.630s	10.100us	0	1	0.00
		chip_sw_example_manufacturer	2.534m		0	1	0.00
		chip_sw_example_concurrency	5.240m	5.117ms	1	1	100.00
		chip_sw_uart_smoketest_signed	11.972s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	9.840s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	8.990s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	8.990s		0	1	0.00
V1	xbar_smoke	xbar_smoke	17.440s	56.720us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.635m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	11.838m	9.311ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	6.798m	5.956ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	12.156s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	15.431s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	12.896s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	11.963s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.100s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.100s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	1.897m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.744m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.013m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.013m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.678m	4.470ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.549m	3.619ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	5.321m	14.949ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	13.190s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	13.956s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	16.765m	25.457ms	0	1	0.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.688m	4.746ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	22.209m	18.027ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	22.209m	18.027ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	12.189s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.192m	3.939ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.192m	3.939ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	8.405m	18.019ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.027m	4.071ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	6.740m	4.355ms	1	1	100.00
		chip_sw_aes_idle	4.007m	3.844ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.606m	5.652ms	1	1	100.00
		chip_sw_kmac_idle	3.424m	3.195ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	13.177m	12.019ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	14.496m	12.019ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	13.796m	12.019ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	14.629m	11.979ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	12.228s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	15.623s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.836s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	16.532s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.489s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.741s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.731s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	12.228s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	15.623s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.836s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	16.532s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.489s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.741s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.731s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	14.528s		0	1	0.00
		chip_sw_aes_enc_jitter_en	38.780s	10.400us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	36.490s	10.140us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	41.380s	10.280us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	39.140s	10.260us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	15.155s		0	1	0.00
		chip_sw_clkmgr_jitter	4.131m	4.108ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.457m	3.930ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	21.374s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	37.460s	10.100us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	42.880s	10.360us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	36.690s	10.360us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	45.830s	10.380us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	35.760s	10.200us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	14.102s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	12.636s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.751s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	11.432s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	20.839m	14.982ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	9.596m	15.346ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	4.192m	3.939ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	14.958s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	9.596m	15.346ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	14.426s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	12.901s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	11.984s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	14.053s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	16.529s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	20.839m	14.982ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	5.321m	14.949ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	24.416m	20.027ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	6.509m	8.244ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	8.102m	8.586ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.569m	4.608ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	20.839m	14.982ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	14.584s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	12.217s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	20.839m	14.982ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	14.172s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	8.102m	8.586ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	15.004s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	12.435s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	13.966s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	13.238s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	15.153s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	13.040s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	12.217s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	11.791s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	17.861s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	11.791s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	11.791s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	11.791s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	8.424m	9.388ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	14.274s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	17.410s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	14.836s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	14.249s		0	1	0.00
		chip_sw_lc_ctrl_transition	11.791s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	6.794m	9.303ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	8.583m	10.773ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	12.596s		0	1	0.00
		chip_prim_tl_access	16.075m	18.783ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	12.228s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	15.623s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.836s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	16.532s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.489s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.741s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.731s		0	1	0.00
		chip_rv_dm_lc_disabled	16.765m	25.457ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.674m	5.660ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	38.780s	10.400us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.362m	5.111ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.007m	3.844ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.930m	4.927ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	36.490s	10.140us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.606m	5.652ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.689m	4.387ms	1	1	100.00
		chip_sw_kmac_mode_kmac	5.647m	5.217ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	39.140s	10.260us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	6.794m	9.303ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	11.791s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	30.890s	10.140us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	6.445m	3.963ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.424m	3.195ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	17.100s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	17.100s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	14.782s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	5.327m	5.026ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	11.703s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	6.794m	9.303ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	41.380s	10.280us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	15.929s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	14.528s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	6.740m	4.355ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	6.740m	4.355ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	6.740m	4.355ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	10.108m	6.622ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.583m	10.773ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.583m	10.773ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	9.595m	7.224ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	15.155s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	12.596s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	20.839m	14.982ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.013m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	11.791s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	10.108m	6.622ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.794m	9.303ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	9.595m	7.224ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.921m	3.599ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	10.108m	6.622ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.794m	9.303ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	9.595m	7.224ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.921m	3.599ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	11.791s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	12.840s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	17.861s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	14.274s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	17.410s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	14.836s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	14.249s		0	1	0.00
		chip_sw_lc_ctrl_transition	11.791s		0	1	0.00
		chip_prim_tl_access	16.075m	18.783ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	16.075m	18.783ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	13.569s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	12.780s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	12.636s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	14.528s		0	1	0.00
		chip_sw_aes_enc_jitter_en	38.780s	10.400us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	36.490s	10.140us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	41.380s	10.280us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	39.140s	10.260us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	15.155s		0	1	0.00
		chip_sw_clkmgr_jitter	4.131m	4.108ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	8.137m	7.213ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	8.137m	7.213ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	5.003m	3.991ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	3.623m	4.031ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	4.263m	4.696ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.830m	6.175ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	5.672m	5.378ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.438m	5.182ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.921m	3.599ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	24.416m	20.027ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	24.416m	20.027ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.573m	4.477ms	1	1	100.00
		chip_sw_aon_timer_smoketest	4.037m	4.475ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.993m	3.516ms	1	1	100.00
		chip_sw_csrng_smoketest	3.032m	4.425ms	1	1	100.00
		chip_sw_gpio_smoketest	4.208m	5.133ms	1	1	100.00
		chip_sw_hmac_smoketest	4.379m	4.633ms	1	1	100.00
		chip_sw_kmac_smoketest	3.911m	3.743ms	1	1	100.00
		chip_sw_otbn_smoketest	5.552m	5.142ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.587m	5.068ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.636m	4.716ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.860m	4.889ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.495m	4.425ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.281m	4.799ms	1	1	100.00
		chip_sw_uart_smoketest	3.571m	5.253ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	11.868s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	11.972s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.635m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	13.543s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.163m	3.995ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.354m	4.187ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.945m	6.223ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.064m	4.838ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	12.269s		0	1	0.00
		chip_rv_dm_lc_disabled	16.765m	25.457ms	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	13.522s		0	1	0.00
		chip_sw_lc_walkthrough_prod	12.244s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	12.341s		0	1	0.00
		chip_sw_lc_walkthrough_rma	13.051s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	12.269s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	14.043s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	12.879s		0	1	0.00
		rom_volatile_raw_unlock	11.152s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	11.541s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	27.005s		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.369m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	3.424m	4.160ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	3.424m	4.160ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	8.990s		0	1	0.00
		chip_same_csr_outstanding	9.570s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	8.990s		0	1	0.00
		chip_same_csr_outstanding	9.570s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	32.400s	35.067us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	9.340s	12.154us	1	1	100.00
		xbar_smoke_large_delays	5.198m	2.694ms	1	1	100.00
		xbar_smoke_slow_rsp	4.988m	1.799ms	1	1	100.00
		xbar_random_zero_delays	34.720s	32.238us	1	1	100.00
		xbar_random_large_delays	3.926m	2.018ms	1	1	100.00
		xbar_random_slow_rsp	7.028m	2.516ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	6.970s	7.367us	1	1	100.00
		xbar_error_and_unmapped_addr	57.600s	42.049us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	46.200s	139.247us	1	1	100.00
		xbar_error_and_unmapped_addr	57.600s	42.049us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.426m	68.772us	1	1	100.00
		xbar_access_same_device_slow_rsp	27.546m	10.322ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.349m	227.994us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	10.537m	1.557ms	1	1	100.00
		xbar_stress_all_with_error	8.549m	1.441ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	19.395m	1.535ms	1	1	100.00
		xbar_stress_all_with_reset_error	25.683m	1.226ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	13.461s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	12.333s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	12.872s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	11.828s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	12.202s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	11.546s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	12.132s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	15.784s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	12.789s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	11.622s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	11.557s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	13.064s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	13.615s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	55.384s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	1.020m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	41.818s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	41.055s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	43.659s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	47.922s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	49.984s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	41.409s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	46.574s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	42.697s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	39.103s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	37.151s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	38.237s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	33.794s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	33.863s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	16.468s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	13.647s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	15.384s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	13.748s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	13.137s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	11.941s		0	1	0.00
		rom_e2e_asm_init_dev	12.808s		0	1	0.00
		rom_e2e_asm_init_prod	11.995s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.732s		0	1	0.00
		rom_e2e_asm_init_rma	12.633s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	11.332s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	11.619s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	11.702s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	12.636s		0	1	0.00
V2		TOTAL			65	205	31.71
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.393m	5.107ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.986m	4.579ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	12.031s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.057s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.425s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	12.563s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	20.839m	14.982ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	12.060s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	19.171m	16.535ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	11.760s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	13.687s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	12.031s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.057s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.425s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.572s		0	1	0.00
		rom_e2e_jtag_inject_dev	12.087s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.738s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	11.643s		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	23.679m	15.213ms	1	1	100.00
		chip_sw_entropy_src_kat_test	5.659m	5.534ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	3.509m	5.183ms	1	1	100.00
		chip_plic_all_irqs_0	10.463m	7.507ms	1	1	100.00
		chip_plic_all_irqs_10	10.945m	6.808ms	1	1	100.00
		chip_sw_dma_inline_hashing	5.648m	5.169ms	1	1	100.00
		chip_sw_dma_abort	5.208m	5.854ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	12.065s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	11.311s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	11.312s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	12.047s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	12.733s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.697s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	11.444s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.442s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	11.262s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	11.778s		0	1	0.00
		chip_sw_entropy_src_smoketest	5.163m	5.085ms	1	1	100.00
		chip_sw_mbx_smoketest	4.352m	5.198ms	1	1	100.00
		TOTAL			79	250	31.60

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.48909195503214690929957682153542765900412668038948315224334030565665458224303
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 138.749s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.39919638628767342040271188981728387598676314986052855691815157650903196046261
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 109.299s, Critical Path: 0.03s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.34839099851781349291965070507990171333417454057201290478272761562457043580954
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 102.727s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.94585425354375735463497956593252068994538513804147853100825709570565855283583
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 93.718s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.86628628759696520467428097202304388436889898481776096505942256025674069779848
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 92.640s, Critical Path: 0.00s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.91458443911571911916121508678440748690499010055647086769795374667724158656486
    Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.26956299033073262830087882031033615795018026014623785339590524232795417986808
    Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.89919868855449269619665912999125003171840559282172808231289814207719182415707
    Line 378, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.56556452970068387337221146525409860974468124739584674236781316430095831647115
    Line 380, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.114661778213771969554393431264370180597409982788981091823587091517689661178649
    Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 4 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.39335695183616605991574470421048634860838787628707700491508507053141163575646
Line 417, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20026.853037 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20026.853037 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.17301846256471644595749421369360982286874441436251080071391363236409096054127
Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18026.983705 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18026.983705 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.45251990362007542117478374331737048656966638249246173683216133018787518666515
Line 388, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18018.668038 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.668038 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.17933878752441244413381903492800748256311838894455065470138902571423864680713
Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12018.608040 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.608040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.56395624977821546638203143339212009918081496551983779476123922243672405827112
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.31434424055523031716569094482905825322972709327446344680957404053898557029080
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.98157438561052012765523908797792654020083688121606075822037492039008281454266
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.95517745274169375205211113862861893138722725331070710482253242572737348225733
Line 405, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 9302.682266 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (12479872908016070775752328877525273433009153971636766654533789936691542208740975509227144557586231237541836293649225087120599415514061815268820372622236764 [0xee48591caae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3681ee9ed7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 9302.682266 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.79960098810277727229442956026286389914214053044199920784731777680444364407931
Line 404, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 9388.302396 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (12994139768356269224143008321287069852499667022648141188688702403199641228553846028414779762271571522195302031043132117272947461020778536121778795255782492 [0xf81a083aaae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd37e4cb8cb7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 9388.302396 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 2 failures:
- Test chip_sw_clkmgr_off_hmac_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_hmac_trans.20818189122303667215941893799113586527159383587222596503071934758183225372879
    Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log
```
  UVM_ERROR @ 12018.509683 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.509683 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_clkmgr_off_kmac_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_kmac_trans.67860620437002106307752165119197467814642953248831149076429786463931298038387
    Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log
```
  UVM_ERROR @ 12018.565000 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.565000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47283) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.36522786541430776061877040743506573086610768612473970354294252047384820089756
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4470.261048 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47283) { a_addr: 'h30480000  a_data: 'h17394a01  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3  a_opcode: 'h1  a_user: 'h248ca  d_param: 'h0  d_source: 'h3  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4470.261048 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.18433076855749449732285538512765948876154556225129874070884573373050564836109
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3619.027130 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47283) { a_addr: 'h30480000  a_data: 'hd938ce82  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h5  a_opcode: 'h1  a_user: 'h2488f  d_param: 'h0  d_source: 'h5  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3619.027130 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.103749915330792154297028840525671619880188332510849492703181173789770564641720
    Line 1375, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.33469524441545055598514757736756976948450509507969572438930903514615382164557
    Line 407, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5956.325178 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5956.325178 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.9264662737115681209157341535942311861674914279269314023252225620372380552536
    Line 634, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 8585.733655 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 8585.733655 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.76592528209074098816867855691618684087566624153892992949037289409536443812620
    Line 387, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 3990.860488 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 3990.860488 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.3972235691068300004288354610813410418037309347975172198720805238291162758306
    Line 386, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4031.460668 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4031.460668 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.53588499640078059772082496749739747217261077185517976177101987649810573220692
    Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 3939.071832 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 3939.071832 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.105222962964252618799058746211374611457166349892077366081102060585986765925507
    Line 403, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 6174.785320 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 6174.785320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.76663797680599105079873328444835987813345921511917076106257793552768173960655
    Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.1931322213937729078083103924344757930237379896199514126088298987315480636174
    Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 4159.929944 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 4159.929944 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.92127348582516407576094752987335895774931180977083033303872347313495444845896
    Line 376, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 14949.103216 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 14949.103216 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.14005797957190538916917319978843062367608731101414450610737622523009014168752
    Line 264, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 25456.627817 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x406f0 read out mismatch
  UVM_INFO @ 25456.627817 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.79472119744772262732112799443165362361089683040597151180321932546489191055282
    Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.67043687393672563551998686185462768169088715398416724986017403261022250216337
    Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 5854.172936 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 5854.172936 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```