AES/MASKED Simulation Results

Monday October 13 2025 16:01:27 UTC

GitHub Revision: `49342f8`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	61.066us	1	1	100.00
V1	smoke	aes_smoke	2.000s	137.335us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	2.000s	94.215us	1	1	100.00
V1	csr_rw	aes_csr_rw	2.000s	67.138us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	4.000s	516.943us	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	3.000s	407.095us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	2.000s	125.547us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	2.000s	67.138us	1	1	100.00
		aes_csr_aliasing	3.000s	407.095us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	2.000s	137.335us	1	1	100.00
		aes_config_error	3.000s	100.240us	1	1	100.00
		aes_stress	3.000s	114.067us	1	1	100.00
V2	key_length	aes_smoke	2.000s	137.335us	1	1	100.00
		aes_config_error	3.000s	100.240us	1	1	100.00
		aes_stress	3.000s	114.067us	1	1	100.00
V2	back2back	aes_stress	3.000s	114.067us	1	1	100.00
		aes_b2b	3.000s	95.153us	1	1	100.00
V2	backpressure	aes_stress	3.000s	114.067us	1	1	100.00
V2	multi_message	aes_smoke	2.000s	137.335us	1	1	100.00
		aes_config_error	3.000s	100.240us	1	1	100.00
		aes_stress	3.000s	114.067us	1	1	100.00
		aes_alert_reset	3.000s	186.514us	1	1	100.00
V2	failure_test	aes_man_cfg_err	3.000s	55.254us	1	1	100.00
		aes_config_error	3.000s	100.240us	1	1	100.00
		aes_alert_reset	3.000s	186.514us	1	1	100.00
V2	trigger_clear_test	aes_clear	5.000s	295.924us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	8.000s	888.739us	1	1	100.00
V2	reset_recovery	aes_alert_reset	3.000s	186.514us	1	1	100.00
V2	stress	aes_stress	3.000s	114.067us	1	1	100.00
V2	sideload	aes_stress	3.000s	114.067us	1	1	100.00
		aes_sideload	6.000s	244.750us	1	1	100.00
V2	deinitialization	aes_deinit	3.000s	370.144us	1	1	100.00
V2	stress_all	aes_stress_all	27.000s	1.991ms	1	1	100.00
V2	alert_test	aes_alert_test	2.000s	106.583us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	2.000s	80.809us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	2.000s	80.809us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	2.000s	94.215us	1	1	100.00
		aes_csr_rw	2.000s	67.138us	1	1	100.00
		aes_csr_aliasing	3.000s	407.095us	1	1	100.00
		aes_same_csr_outstanding	1.000s	70.960us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	2.000s	94.215us	1	1	100.00
		aes_csr_rw	2.000s	67.138us	1	1	100.00
		aes_csr_aliasing	3.000s	407.095us	1	1	100.00
		aes_same_csr_outstanding	1.000s	70.960us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	4.000s	164.689us	1	1	100.00
V2S	fault_inject	aes_fi	4.000s	222.583us	1	1	100.00
		aes_control_fi	2.000s	70.037us	1	1	100.00
		aes_cipher_fi	1.000s	65.674us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	2.000s	83.709us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	2.000s	83.709us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	2.000s	83.709us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	2.000s	83.709us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	2.000s	168.624us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	5.000s	596.125us	1	1	100.00
		aes_tl_intg_err	2.000s	147.890us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	2.000s	147.890us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	3.000s	186.514us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	2.000s	83.709us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	2.000s	137.335us	1	1	100.00
		aes_stress	3.000s	114.067us	1	1	100.00
		aes_alert_reset	3.000s	186.514us	1	1	100.00
		aes_core_fi	1.000s	9.137us	0	1	0.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	2.000s	83.709us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	2.000s	84.834us	1	1	100.00
		aes_stress	3.000s	114.067us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	3.000s	114.067us	1	1	100.00
		aes_sideload	6.000s	244.750us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	2.000s	84.834us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	2.000s	84.834us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	2.000s	84.834us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	2.000s	84.834us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	2.000s	84.834us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	3.000s	114.067us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	3.000s	114.067us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	4.000s	222.583us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	4.000s	222.583us	1	1	100.00
		aes_control_fi	2.000s	70.037us	1	1	100.00
		aes_cipher_fi	1.000s	65.674us	1	1	100.00
		aes_ctr_fi	3.000s	188.461us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	4.000s	222.583us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	4.000s	222.583us	1	1	100.00
		aes_control_fi	2.000s	70.037us	1	1	100.00
		aes_cipher_fi	1.000s	65.674us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	1.000s	65.674us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	4.000s	222.583us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	4.000s	222.583us	1	1	100.00
		aes_control_fi	2.000s	70.037us	1	1	100.00
		aes_ctr_fi	3.000s	188.461us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	4.000s	222.583us	1	1	100.00
		aes_control_fi	2.000s	70.037us	1	1	100.00
		aes_cipher_fi	1.000s	65.674us	1	1	100.00
		aes_ctr_fi	3.000s	188.461us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	3.000s	186.514us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	4.000s	222.583us	1	1	100.00
		aes_control_fi	2.000s	70.037us	1	1	100.00
		aes_cipher_fi	1.000s	65.674us	1	1	100.00
		aes_ctr_fi	3.000s	188.461us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	4.000s	222.583us	1	1	100.00
		aes_control_fi	2.000s	70.037us	1	1	100.00
		aes_cipher_fi	1.000s	65.674us	1	1	100.00
		aes_ctr_fi	3.000s	188.461us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	4.000s	222.583us	1	1	100.00
		aes_control_fi	2.000s	70.037us	1	1	100.00
		aes_ctr_fi	3.000s	188.461us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	4.000s	222.583us	1	1	100.00
		aes_control_fi	2.000s	70.037us	1	1	100.00
		aes_cipher_fi	1.000s	65.674us	1	1	100.00
V2S		TOTAL			10	11	90.91
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	23.000s	498.974us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			30	32	93.75

Failure Buckets

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_cipher_core.sv,858): Assertion AesSecCmKeyMaskingInitialPrngUpdateSubBytes has failed (* cycles, starting * PS) has 1 failures:

Test aes_core_fi has 1 failures.

0.aes_core_fi.68216426453240578538195134538864316374544453071855308907163394119937649641532
Line 132, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_core_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_core.sv,858): (time 9136952 PS) Assertion tb.dut.u_aes_core.u_aes_cipher_core.gen_sec_cm_key_masking_svas.AesSecCmKeyMaskingInitialPrngUpdateSubBytes has failed (2 cycles, starting 9126952 PS)
  UVM_ERROR @   9136952 ps: (aes_cipher_core.sv:858) [ASSERT FAILED] AesSecCmKeyMaskingInitialPrngUpdateSubBytes
  UVM_INFO @   9136952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 0.aes_stress_all_with_rand_reset.1324671096353814605755497508239323989371750833396852842711905870557962655859
    Line 823, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 498974038 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 498974038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```