| V1 |
smoke |
aon_timer_smoke |
1.210s |
614.747us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
aon_timer_csr_hw_reset |
2.120s |
1.283ms |
1 |
1 |
100.00 |
| V1 |
csr_rw |
aon_timer_csr_rw |
0.960s |
340.545us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
aon_timer_csr_bit_bash |
4.370s |
7.681ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
aon_timer_csr_aliasing |
1.430s |
516.915us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
aon_timer_csr_mem_rw_with_rand_reset |
0.900s |
520.819us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
aon_timer_csr_rw |
0.960s |
340.545us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_aliasing |
1.430s |
516.915us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
aon_timer_mem_walk |
0.730s |
514.334us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
aon_timer_mem_partial_access |
0.810s |
328.028us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
prescaler |
aon_timer_prescaler |
9.190s |
32.227ms |
1 |
1 |
100.00 |
| V2 |
jump |
aon_timer_jump |
1.410s |
636.310us |
1 |
1 |
100.00 |
| V2 |
stress_all |
aon_timer_stress_all |
6.750s |
36.473ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
aon_timer_alert_test |
0.920s |
293.745us |
1 |
1 |
100.00 |
| V2 |
intr_test |
aon_timer_intr_test |
0.810s |
472.094us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
aon_timer_tl_errors |
1.560s |
577.016us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
aon_timer_tl_errors |
1.560s |
577.016us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
aon_timer_csr_hw_reset |
2.120s |
1.283ms |
1 |
1 |
100.00 |
|
|
aon_timer_csr_rw |
0.960s |
340.545us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_aliasing |
1.430s |
516.915us |
1 |
1 |
100.00 |
|
|
aon_timer_same_csr_outstanding |
2.260s |
1.906ms |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
aon_timer_csr_hw_reset |
2.120s |
1.283ms |
1 |
1 |
100.00 |
|
|
aon_timer_csr_rw |
0.960s |
340.545us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_aliasing |
1.430s |
516.915us |
1 |
1 |
100.00 |
|
|
aon_timer_same_csr_outstanding |
2.260s |
1.906ms |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
7 |
7 |
100.00 |
| V2S |
tl_intg_err |
aon_timer_sec_cm |
2.100s |
4.105ms |
1 |
1 |
100.00 |
|
|
aon_timer_tl_intg_err |
5.820s |
4.547ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
aon_timer_tl_intg_err |
5.820s |
4.547ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
max_threshold |
aon_timer_smoke_max_thold |
0.860s |
764.175us |
1 |
1 |
100.00 |
| V3 |
min_threshold |
aon_timer_smoke_min_thold |
1.680s |
729.395us |
1 |
1 |
100.00 |
| V3 |
wkup_count_hi_cdc |
aon_timer_wkup_count_cdc_hi |
2.130s |
3.418ms |
1 |
1 |
100.00 |
| V3 |
custom_intr |
aon_timer_custom_intr |
0.840s |
674.076us |
1 |
1 |
100.00 |
| V3 |
alternating_on_off |
aon_timer_alternating_enable_on_off |
13.180s |
4.094ms |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
aon_timer_stress_all_with_rand_reset |
22.740s |
4.905ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
|
|
TOTAL |
|
|
23 |
23 |
100.00 |