DMA Simulation Results

Monday October 13 2025 16:01:27 UTC

GitHub Revision: 49342f8

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	6.000s	485.784us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	4.000s	286.229us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	4.000s	955.756us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	1.000s	61.015us	1	1	100.00
V1	csr_rw	dma_csr_rw	2.000s	36.585us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	9.000s	606.004us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	5.000s	907.389us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	1.000s	54.049us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	2.000s	36.585us	1	1	100.00
		dma_csr_aliasing	5.000s	907.389us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.267m	4.014ms	1	1	100.00
V2	dma_memory_tl_error	dma_memory_stress	10.983m	174.242ms	1	1	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	59.000s	9.974ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	59.000s	9.974ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	10.983m	174.242ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	8.350m	208.612ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	59.000s	9.974ms	1	1	100.00
V2	dma_abort	dma_abort	10.000s	9.292ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	1.150m	6.007ms	1	1	100.00
V2	alert_test	dma_alert_test	1.000s	42.555us	1	1	100.00
V2	intr_test	dma_intr_test	2.000s	18.797us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	2.000s	53.510us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	2.000s	53.510us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	1.000s	61.015us	1	1	100.00
		dma_csr_rw	2.000s	36.585us	1	1	100.00
		dma_csr_aliasing	5.000s	907.389us	1	1	100.00
		dma_same_csr_outstanding	2.000s	47.593us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	1.000s	61.015us	1	1	100.00
		dma_csr_rw	2.000s	36.585us	1	1	100.00
		dma_csr_aliasing	5.000s	907.389us	1	1	100.00
		dma_same_csr_outstanding	2.000s	47.593us	1	1	100.00
V2		TOTAL			10	10	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	13.000s	198.938us	1	1	100.00
		dma_generic_stress	8.350m	208.612ms	1	1	100.00
		dma_handshake_stress	59.000s	9.974ms	1	1	100.00
V2S	dma_config_lock	dma_config_lock	8.000s	1.855ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	3.000s	253.676us	1	1	100.00
		dma_sec_cm	1.000s	12.853us	1	1	100.00
V2S		TOTAL			4	4	100.00
	Unmapped tests	dma_short_transfer	1.550m	43.143ms	1	1	100.00
		dma_longer_transfer	3.000s	214.043us	1	1	100.00
		dma_stress_all_with_rand_reset	12.000s	570.368us	0	1	0.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.104735608134036381440446617466511820149246441464723360605845109147741940375072
      Line 108, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  570367702ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @  570367702ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---