EDN Simulation Results

Monday October 13 2025 16:01:27 UTC

GitHub Revision: 49342f8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.990s	17.750us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.960s	16.090us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.810s	14.721us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	2.200s	781.813us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.070s	40.220us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.060s	26.956us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.810s	14.721us	1	1	100.00
		edn_csr_aliasing	1.070s	40.220us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.020s	115.322us	1	1	100.00
V2	csrng_commands	edn_genbits	1.020s	115.322us	1	1	100.00
V2	genbits	edn_genbits	1.020s	115.322us	1	1	100.00
V2	interrupts	edn_intr	0.910s	62.681us	1	1	100.00
V2	alerts	edn_alert	1.090s	46.529us	1	1	100.00
V2	errs	edn_err	1.090s	18.968us	1	1	100.00
V2	disable	edn_disable	0.860s	28.883us	1	1	100.00
		edn_disable_auto_req_mode	0.940s	63.080us	1	1	100.00
V2	stress_all	edn_stress_all	1.140s	99.421us	1	1	100.00
V2	intr_test	edn_intr_test	0.930s	14.692us	1	1	100.00
V2	alert_test	edn_alert_test	0.970s	35.279us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.470s	388.834us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.470s	388.834us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.960s	16.090us	1	1	100.00
		edn_csr_rw	0.810s	14.721us	1	1	100.00
		edn_csr_aliasing	1.070s	40.220us	1	1	100.00
		edn_same_csr_outstanding	0.870s	13.715us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.960s	16.090us	1	1	100.00
		edn_csr_rw	0.810s	14.721us	1	1	100.00
		edn_csr_aliasing	1.070s	40.220us	1	1	100.00
		edn_same_csr_outstanding	0.870s	13.715us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	3.470s	1.117ms	1	1	100.00
		edn_tl_intg_err	1.260s	544.774us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.840s	30.549us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.090s	46.529us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	3.470s	1.117ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	3.470s	1.117ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	3.470s	1.117ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	3.470s	1.117ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.090s	46.529us	1	1	100.00
		edn_sec_cm	3.470s	1.117ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.090s	46.529us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	1.260s	544.774us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.230m	4.640ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00